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ADSP-21266SKBC-200X PDF预览

ADSP-21266SKBC-200X

更新时间： 2024-11-30 15:44:55
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 1410K
描述
IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC

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ADSP-21266SKBC-200X 数据手册

 浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第2页浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第3页浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第4页浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第5页浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第6页浏览型号ADSP-21266SKBC-200X的Datasheet PDF文件第7页 
PRELIMINARY TECHNICAL DATA  
S
a
High Performance SHARC Audio Processor  
ADSP-21266  
DAI incorporates a Precision Clock Generator (PCG), and  
an Input Data Port (IDP) that includes a Parallel Data  
Acquisition Port (PDAP), all under software control by  
the Signal Routing Unit (SRU)  
On-chip memory — 2 Mbits of on-chip SRAM and a  
dedicated 4 Mbits of on-chip mask-programmable  
ROM  
Preliminary Technical Data  
SUMMARY  
High performance 32-bit/40-bit floating point processor  
optimized for audio processing  
The ADSP-21266 processes high performance audio  
while enabling low system costs  
Audio decoder and post processor-algorithm support.  
Non-volatile memory can be configured to contain a  
combination of PCM 96kHz, Dolby Digital, Dolby  
Digital EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1,  
DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, Dolby  
Pro Logic II and DTS Neo:6  
Single-Instruction Multiple-Data (SIMD) computational  
architecture—two 32-bit IEEE floating-point/32-bit  
fixed point/ 40-bit extended precision floating point  
computational units, each with a multiplier, ALU,  
shifter, and register file  
Serial ports offer Left-justified Sample Pair and I2S  
support via 12 programmable and simultaneous  
receive or transmit pins, which support up to 24  
transmit or 24 receive I2S channels of audio when all  
6 Serial Ports (SPORTs) are enabled or 6 full duplex  
TDM streams of up to 128 channels per frame  
The ADSP-21266 is available with a 150 MHz or a  
200MHz core instruction rate. For complete ordering  
information, see Ordering Guide on page 43  
High bandwidth I/O — a parallel port, SPI port, 6 serial  
ports, a digital audio interface (DAI) and JTAG  
FUNCTIONAL BLOCK DIAGRAM  
CORE PROCESSOR  
DUAL-PORTED SRAM  
DUAL-PORTED ROM  
TWO INDEPENDENT  
INSTRUCTION  
CACHE  
32 X 48-BIT  
TWO INDEPENDENT  
BLOCKS  
BLOCKS  
TIMER  
ADDR  
DATA  
DATA  
ADDR  
ADDR  
DATA  
ADDR  
DATA  
DATA  
ADDR  
ADDR  
DATA  
DAG1  
8X4X32  
DAG2  
8X4X32  
PROGRAM  
SEQUENCER  
IOD  
32  
IOA  
18  
32  
PM ADDRESS BUS  
32  
64  
DM ADDRESS BUS  
PM DATA BUS  
PX REGISTER  
64  
DM DATA BUS  
6
4
JTAG TEST & EMULATION  
GPIO FLAGS/IRQ/TIMEXP  
DMA CONTROLLER  
22 CHANNELS  
PARALLEL PORT  
DATA  
REGISTER  
FI LE  
(PEX)  
DATA  
REGISTER  
FILE  
(PEY)  
IOP  
RE GIS TE RS  
(MEMORY MAPPED)  
16  
3
ADDRES S/DATA BUS / GP IO  
C ONT RO L/GPIO  
BARREL  
SHIFTER  
BARREL  
SHIFTER  
16 X 40-BIT  
16 X 40-BIT  
CONTROL,  
STATUS, &  
4
MULT  
MULT  
SPI PORT (1)  
DATA BUFFE RS  
SERIAL PORTS (6)  
SIGNAL  
ROUTING  
UNIT  
ALU  
ALU  
INPUT  
DATA PO RT (8)  
20  
PRECISION CLOCK  
GENERATOR (1)  
DAI  
3
TIMERS (3)  
I/O PROCESSOR  
REV. PrB  
This information applies to a product under development. Its characteristics and One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.  
specifications are subject to change without notice. Analog Devices assumes Tel:781/329-4700  
no obligation regarding future manufacturing unless otherwise agreed to in Fax:781/326-8703  
writing.  
www.analog.com  
©Analog Devices,Inc., 2003  
1234567...44

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