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ADSP-21160N_15 PDF预览

ADSP-21160N_15

更新时间: 2022-02-26 13:50:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1205K
描述
SHARC Digital Signal Processor

ADSP-21160N_15 数据手册

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SHARC  
Digital Signal Processor  
ADSP-21160M/ADSP-21160N  
SUMMARY  
FEATURES  
High performance 32-bit DSP—applications in audio, medi-  
cal, military, graphics, imaging, and communication  
Super Harvard architecture—4 independent buses for dual  
data fetch, instruction fetch, and nonintrusive, zero-over-  
head I/O  
100 MHz (10 ns) core instruction rate (ADSP-21160N)  
Single-cycle instruction execution, including SIMD opera-  
tions in both computational units  
Dual data address generators (DAGs) with modulo and bit-  
reverse addressing  
Backward compatible—assembly source level compatible  
with code for ADSP-2106x DSPs  
Zero-overhead looping and single-cycle loop setup, provid-  
ing efficient program sequencing  
Single-instruction, multiple-data (SIMD) computational  
architecture—two 32-bit IEEE floating-point computation  
units, each with a multiplier, ALU, shifter, and register file  
Integrated peripherals—integrated I/O processor, 4M bits  
on-chip dual-ported SRAM, glueless multiprocessing fea-  
tures, and ports (serial, link, external bus, and JTAG)  
IEEE 1149.1 JTAG standard Test Access Port and on-chip  
emulation  
400-ball 27 mm × 27 mm PBGA package  
Available in lead-free (RoHS compliant) package  
200 million fixed-point MACs sustained performance  
(ADSP-21160N)  
CORE PROCESSOR  
DUAL-PORTED SRAM  
JTAG  
INSTRUCTION  
CACHE  
32 x 48-BIT  
TIMER  
TWO INDEPENDENT  
6
DUAL-PORTED BLOCKS  
TEST AND  
EMULATION  
PROCESSOR PORT  
ADDR DATA  
ADDR  
I/O PORT  
DATA ADDR  
DATA  
ADDR  
DATA  
DAG2  
8 x 4 x 32  
DAG1  
8 x 4 x 32  
PROGRAM  
SEQUENCER  
EXTERNAL  
PORT  
IOD  
64  
IOA  
18  
PM ADDRESS BUS  
32  
32  
32  
64  
ADDR BUS  
MUX  
DM ADDRESS BUS  
MULTIPROCESSOR  
INTERFACE  
PM DATA BUS  
DM DATA BUS  
16/32/40/48/64  
32/40/64  
BUS  
CONNECT  
(PX)  
DATA BUS  
MUX  
HOST PORT  
DATA  
REGISTER  
FILE  
DATA  
REGISTER  
FILE  
4
(PEX)  
16 x 40-BIT  
(PEY)  
16 x 40-BIT  
DMA  
CONTROLLER  
IOP  
BARREL  
SHIFTER  
BARREL  
SHIFTER  
MULT  
MULT  
REGISTERS  
(MEMORY  
MAPPED)  
6
6
SERIAL PORTS  
(2)  
CONTROL,  
STATUS AND  
DATA BUFFERS  
60  
LINK PORTS  
(6)  
ALU  
ALU  
I/O PROCESSOR  
Figure 1. Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. C Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  

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