Datasheet > ADSP-21160N_15

ADSP-21160N_15

更新时间： 2022-02-26 13:50:54

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
60页	1205K
描述
SHARC Digital Signal Processor

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ADSP-21160N_15 数据手册

ADSP-21160M/ADSP-21160N

TABLE OF CONTENTS

Summary ............................................................... 1

Features ................................................................. 1

General Description ................................................. 4

ADSP-21160x Family Core Architecture .................... 4

Memory and I/O Interface Features ........................... 7

Development Tools ............................................... 9

Additional Information ......................................... 10

Related Signal Chains ........................................... 10

Pin Function Descriptions ........................................ 11

Specifications ......................................................... 15

Operating Conditions—ADSP-21160M .................... 15

Electrical Characteristics—ADSP-21160M ................. 16

Operating Conditions—ADSP-21160N ..................... 17

Electrical Characteristics—ADSP-21160N ................. 18

Absolute Maximum Ratings ................................... 19

ESD Sensitivity ................................................... 19

Package Information ............................................ 19

Timing Specifications ........................................... 20

Output Drive Currents—ADSP-21160M ................... 47

Output Drive Currents—ADSP-21160N ................... 47

Power Dissipation ............................................... 47

Test Conditions .................................................. 48

Environmental Conditions .................................... 51

400-Ball PBGA Pin Configurations ............................. 52

Outline Dimensions ................................................ 57

Surface-Mount Design ............................................. 57

Ordering Guide ..................................................... 58

REVISION HISTORY

2/13—Rev. B to Rev. C

Updated Development Tools ...................................... 9

Added section, Related Signal Chains ..........................10

Added Footnote 4 to Table 18 in

Memory Read—Bus Master .......................................26

Corrected Footnote 2 in Table 40, 400-Ball PBGA Pin Assign-

ments ...................................................................52

Rev. C

Page 3 of 60

February 2013

1 234 5 6 7...60

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