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9ZXL0831

更新时间： 2024-01-27 04:24:56
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件
页数 文件大小 规格书
18页 347K
描述
8-OUTPUT

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中文翻译

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9ZXL0831 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：VFQFPN
包装说明：HVQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.71
系列：9ZXL输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：6 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：48
实输出次数：16最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260Same Edge Skew-Max（tskwd）：0.065 ns
座面最大高度：1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6 mm
Base Number Matches：1

9ZXL0831 数据手册

 浏览型号9ZXL0831的Datasheet PDF文件第5页浏览型号9ZXL0831的Datasheet PDF文件第6页浏览型号9ZXL0831的Datasheet PDF文件第7页浏览型号9ZXL0831的Datasheet PDF文件第9页浏览型号9ZXL0831的Datasheet PDF文件第10页浏览型号9ZXL0831的Datasheet PDF文件第11页 
9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
Input-to-Output Skew in PLL mode  
nominal value @ 25°C, 3.3V  
MIN  
-100  
TYP  
-60  
MAX  
100  
UNITS NOTES  
CLK_IN, DIF[x:0]  
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
Input-to-Output Skew in Bypass mode  
nominal value @ 25°C, 3.3V  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
2.5  
-50  
3.2  
4.5  
50  
tDSPO_PLL  
Input-to-Output Skew Varation in Bypass mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF{x:0]  
tDSPO_BYP  
-250  
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZX devices in Hi BW Mode  
ps  
(rms)  
tDTE  
1
5
Random Differential Spread Spectrum Tracking  
error beween two 9ZX devices in Hi BW Mode  
tDSSTE  
75  
65  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode)  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
53  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
1.2  
0.76  
3
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
4
MHz  
MHz  
%
0.7  
45  
1.1  
50.1  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-2  
0
2
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
34  
17  
50  
50  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Ω
Ω
CL = 2pF with RS = 27 for Zo = 85 differential trace impedance. Input to output skew is measured at the first output edge following the  
corresponding input.  
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6.t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform  
IDT® 8-OUTPUT DB800ZL  
8
9ZXL0831  
REV E 081616  
1...567891011...18

中文翻译

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