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9ZXL0831 PDF预览

9ZXL0831

更新时间: 2024-02-14 14:21:30
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件
页数 文件大小 规格书
18页 347K
描述
8-OUTPUT

9ZXL0831 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.71
系列:9ZXL输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:6 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:16最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260Same Edge Skew-Max(tskwd):0.065 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

9ZXL0831 数据手册

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9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–Input/Supply/Common Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
TCOM  
CONDITIONS  
MIN  
0
TYP  
MAX  
70  
UNITS NOTES  
Ambient Operating  
Temperature  
Commmercial range  
°C  
V
1
1
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
VDD + 0.3  
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
1
V
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
150  
110  
147  
7
MHz  
MHz  
MHz  
nH  
2
2
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
2
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
Output pin capacitance  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
COUT  
2.7  
6
pF  
1,4  
1
pF  
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Allowable Frequency  
Clk Stabilization  
TSTAB  
fMODIN  
tLATOE#  
tDRVPD  
0.250  
1
ms  
kHz  
1,2  
1
Input SS Modulation  
Frequency  
30  
4
33  
(Triangular Modulation)  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
12  
cycles  
us  
1,3  
1,3  
300  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
10  
10  
ns  
ns  
V
1,2  
1,2  
1
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
VILSMB  
VIHSMB  
VOLSMB  
IPULLUP  
VDDSMB  
tRSMB  
tFSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
1
@ IPULLUP  
@ VOL  
V
1
4
mA  
V
1
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
1
fMAXSMB  
Maximum SMBus operating frequency  
100  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
IDT® 8-OUTPUT DB800ZL  
6
9ZXL0831  
REV E 081616  

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