5秒后页面跳转
捷配首页

Datasheet > 9ZX21901DKLF
9ZX21901DKLF PDF预览

9ZX21901DKLF

更新时间： 2024-02-19 10:59:44
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
20页 341K
描述
19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

阅读下载

获取价格

9ZX21901DKLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：VFQFPN
包装说明：HVQCCN,针数：72
Reach Compliance Code：compliant风险等级：2.29
系列：9ZX输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N72JESD-609代码：e3
长度：10 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：72
实输出次数：38最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260座面最大高度：1 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

9ZX21901DKLF 数据手册

 浏览型号9ZX21901DKLF的Datasheet PDF文件第5页浏览型号9ZX21901DKLF的Datasheet PDF文件第6页浏览型号9ZX21901DKLF的Datasheet PDF文件第7页浏览型号9ZX21901DKLF的Datasheet PDF文件第9页浏览型号9ZX21901DKLF的Datasheet PDF文件第10页浏览型号9ZX21901DKLF的Datasheet PDF文件第11页 
9ZX21901D DATASHEET  
Electrical Characteristics – Skew and Differential Jitter Parameters  
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions  
PARAMETER  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
SYMBOL  
tSPO_PLL  
tPD_BYP  
CONDITIONS  
MIN  
-100  
1.9  
TYP  
54  
MAX UNITS NOTES  
Input-to-Output Skew in PLL mode  
at 100MHz, nominal temperature and voltage  
Input-to-Output Skew in Bypass mode  
at 100MHz, nominal temperature and voltage  
Input-to-Output Skew Variation in PLL mode  
at 100MHz, across voltage and temperature  
Input-to-Output Skew Variation in Bypass  
mode  
100  
3
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
2.6  
0.0  
tDSPO_PLL  
-50  
50  
CLK_IN, DIF[x:0]  
tDSPO_BYP  
-250  
0.0  
250  
ps  
1,2,3,5,8  
at 100MHz, across voltage and temperature,  
T
AMB = TCOM  
Output-to-Output Skew across all outputs,  
DIF[x:0]  
tSKEW_ALL  
32  
50  
ps  
1,2,3,8  
common to PLL and Bypass mode, at 100MHz  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
0
0
1.4  
1.2  
2.8  
1.1  
50  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
2
4
MHz  
MHz  
%
0.7  
45  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode at  
100MHz  
Duty Cycle Distortion  
Jitter, Cycle to Cycle  
tDCD  
-1  
-0.5  
0
%
1,10  
PLL mode  
17  
50  
5
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Additive Jitter in Bypass Mode  
0.1  
1
2
3
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
4 This parameter is deterministic for a given device.  
5
Measured with scope averaging on to find mean value.  
6 t is the period of the input clock.  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform.  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  
8
APRIL 17, 2018  
1...567891011...20

下载PDF

与9ZX21901DKLF相关器件

型号 品牌 描述 获取价格 数据表
9ZX21901DKLFT IDT 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI

获取价格
9ZXL0451E RENESAS 4-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

获取价格
9ZXL0631E IDT 6-Output DB800ZL Derivative for PCIe Gen1–4

获取价格
9ZXL0631E RENESAS 6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

获取价格
9ZXL0631EKILF IDT 6-Output DB800ZL Derivative for PCIe Gen1–4

获取价格
9ZXL0631EKILFT IDT 6-Output DB800ZL Derivative for PCIe Gen1–4

获取价格

与9ZX21901DKLF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证