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9ZX21901D PDF预览

9ZX21901D

更新时间: 2023-12-20 18:45:08
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 608K
描述
Enhanced DB1900Z Compliant 19-Output Buffer

9ZX21901D 数据手册

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Pin Descriptions (cont.)  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
Active low input for enabling DIF pair 6.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 7.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 8.  
1 =disable outputs, 0 = enable outputs  
Ground pin.  
37  
OE6#  
DIF_7  
IN  
38  
39  
OUT  
OUT  
DIF_7#  
40  
OE7#  
IN  
41  
42  
DIF_8  
OUT  
OUT  
DIF_8#  
43  
OE8#  
IN  
44  
45  
46  
47  
GND  
VDD  
GND  
PWR  
OUT  
OUT  
Power supply, nominal 3.3V  
HCSL true clock output  
DIF_9  
DIF_9#  
HCSL Complementary clock output  
Active low input for enabling DIF pair 9.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 10.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 11.  
1 =disable outputs, 0 = enable outputs  
HCSL true clock output  
HCSL Complementary clock output  
Active low input for enabling DIF pair 12.  
1 =disable outputs, 0 = enable outputs  
Power supply, nominal 3.3V  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
HCSL Complementary clock output  
Ground pin.  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
HCSL Complementary clock output  
Power supply, nominal 3.3V  
HCSL true clock output  
HCSL Complementary clock output  
HCSL true clock output  
48  
OE9#  
IN  
49  
50  
DIF_10  
DIF_10#  
OUT  
OUT  
51  
OE10#  
IN  
52  
53  
DIF_11  
DIF_11#  
OUT  
OUT  
54  
OE11#  
IN  
55  
56  
DIF_12  
DIF_12#  
OUT  
OUT  
57  
OE12#  
IN  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
VDD  
PWR  
OUT  
OUT  
OUT  
OUT  
GND  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
DIF_13  
DIF_13#  
DIF_14  
DIF_14#  
GND  
DIF_15  
DIF_15#  
DIF_16  
DIF_16#  
VDD  
DIF_17  
DIF_17#  
DIF_18  
DIF_18#  
HCSL Complementary clock output  
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI  

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