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9ZX21901D

更新时间： 2023-12-20 18:45:08
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 608K
描述
Enhanced DB1900Z Compliant 19-Output Buffer

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9ZX21901D 数据手册

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Pin Descriptions  
PIN #  
1
2
PIN NAME  
VDDA  
GNDA  
PIN TYPE  
PWR  
GND  
DESCRIPTION  
Power supply for PLL core.  
Ground pin for the PLL core.  
This pin establishes the reference for the differential current-mode output pairs.  
It requires a fixed precision resistor to ground. 475ohm is the standard value  
for 100ohm differential impedance. Other impedances require different values.  
See data sheet.  
3
IREF  
OUT  
Input to select operating frequency  
1 = 100MHz, 0 = 133.33MHz  
Tri-level input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
4
5
100M_133M#  
IN  
IN  
HIBW_BYPM_LOBW#  
3.3V input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
6
CKPWRGD_PD#  
IN  
7
8
GND  
GND  
PWR  
Ground pin.  
Power supply for differential input clock (receiver). This VDD should be treated  
as an analog power rail and filtered appropriately. Nominally 3.3V.  
HCSL true input.  
VDDR  
9
10  
DIF_IN  
DIF_IN#  
IN  
IN  
HCSL complementary input.  
SMBus address pin. This is a tri-level input that works in conjunction with other  
SMBus address pins to decode 3^n SMBus addresses, where n is the number  
Data pin of SMBUS circuitry  
11  
SMB_A0_tri  
IN  
12  
13  
SMBDAT  
SMBCLK  
I/O  
IN  
Clock pin of SMBUS circuitry  
SMBus address pin. This is a tri-level input that works in conjunction with other  
SMBus address pins to decode 3^n SMBus addresses, where n is the number  
No connection.  
14  
SMB_A1_tri  
IN  
15  
16  
NC  
NC  
N/A  
N/A  
No connection.  
Complementary half of differential feedback output, provides feedback signal  
to the PLL for synchronization with input clock to eliminate phase error.  
17  
DFB_OUT#  
OUT  
True half of differential feedback output, provides feedback signal to the PLL  
for synchronization with the input clock to eliminate phase error.  
HCSL true clock output.  
HCSL complementary clock output.  
Power supply, nominally 3.3V.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Ground pin.  
HCSL true clock output.  
HCSL complementary clock output.  
HCSL true clock output.  
HCSL complementary clock output.  
Power supply, nominally 3.3V.  
18  
DFB_OUT  
OUT  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
DIF_0  
DIF_0#  
VDD  
DIF_1  
DIF_1#  
DIF_2  
DIF_2#  
GND  
DIF_3  
DIF_3#  
DIF_4  
DIF_4#  
VDD  
OUT  
OUT  
PWR  
OUT  
OUT  
OUT  
OUT  
GND  
OUT  
OUT  
OUT  
OUT  
PWR  
OUT  
OUT  
DIF_5  
DIF_5#  
HCSL true clock output.  
HCSL complementary clock output.  
Active low input for enabling output 5.  
1 = disable outputs, 0 = enable outputs.  
HCSL true clock output.  
34  
OE5#  
IN  
35  
36  
DIF_6  
DIF_6#  
OUT  
OUT  
HCSL complementary clock output.  
APRIL 17, 2018  
1234567...19

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