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9ZX21901CKLFT PDF预览

9ZX21901CKLFT

更新时间： 2024-02-06 06:09:48
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路PC
页数 文件大小 规格书
16页 174K
描述
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

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9ZX21901CKLFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：VFQFPN
包装说明：HVQCCN,针数：72
Reach Compliance Code：compliant风险等级：5.73
Samacsys Description：VFQFP-N 10.0 X 10.0 X 0.9 MM - NO LEAD系列：9ZX
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-XQCC-N72
JESD-609代码：e3长度：10 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：72实输出次数：38
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

9ZX21901CKLFT 数据手册

 浏览型号9ZX21901CKLFT的Datasheet PDF文件第3页浏览型号9ZX21901CKLFT的Datasheet PDF文件第4页浏览型号9ZX21901CKLFT的Datasheet PDF文件第5页浏览型号9ZX21901CKLFT的Datasheet PDF文件第7页浏览型号9ZX21901CKLFT的Datasheet PDF文件第8页浏览型号9ZX21901CKLFT的Datasheet PDF文件第9页 
9ZX21901C  
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
Electrical Characteristics - Clock Input Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
600  
TYP  
750  
MAX  
1150  
UNITS NOTES  
Differential inputs  
(single-ended measurement)  
Differential inputs  
Input High Voltage - DIF_IN  
VIHDIF  
mV  
mV  
mV  
1
1
1
Input Low Voltage - DIF_IN  
VILDIF  
VCOM  
VSS - 300  
300  
0
300  
(single-ended measurement)  
Input Common Mode  
Voltage - DIF_IN  
Common Mode Input Voltage  
1000  
Input Amplitude - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Peak to Peak value  
Measured differentially  
VIN = VDD , VIN = GND  
300  
0.4  
-5  
1450  
8
5
mV  
V/ns  
uA  
1
1,2  
1
Input Duty Cycle  
dtin  
Measurement from differential wavefrom  
Differential Measurement  
45  
0
55  
125  
%
1
Input Jitter - Cycle to Cycle  
JDIFIn  
ps  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
1
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Rise/Fall Time Matching  
dV/dt  
ΔdV/dt  
Scope averaging on  
Slew rate matching, Scope averaging on  
Rise/fall matching, Scope averaging off  
2.5  
4
20  
1, 2, 3  
1, 2, 4  
1, 7, 8  
ps  
Trf  
125  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
660  
750  
850  
1
1
mV  
VLow  
-150  
150  
Max Voltage  
Min Voltage  
Vswing  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vswing  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
1150  
1
1
1, 2  
1, 5  
1, 6  
mV  
-300  
300  
250  
mV  
mV  
mV  
Vcross_abs  
Scope averaging off  
Scope averaging off  
550  
140  
Δ
-Vcross  
1
Ω
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA.  
Ω Ω  
OH = 6 x IREF and VOH = 0.7V @ ZO=50 (100 differential impedance).  
I
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross  
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.  
7 Measured from single-ended waveform  
8 Measured with scope averaging off, using statistics function. Variation is difference between min and max.  
Electrical Characteristics - Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP MAX UNITS NOTES  
Operating Supply Current  
Powerdown Current  
IDD3.3OP  
All outputs active @100MHz, CL = Full load;  
All differential pairs tri-stated  
407  
12  
500  
36  
mA  
mA  
1
1
IDD3.3PDZ  
1Guaranteed by design and characterization, not 100% tested in production.  
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI  
1648H- 12/08/11  
6
1...3456789...16

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