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9DB801GLFT PDF预览

9DB801GLFT

更新时间: 2024-01-02 17:28:16
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
18页 178K
描述
Clock Driver, PDSO48

9DB801GLFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G48
JESD-609代码:e3湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
子类别:Clock Drivers标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

9DB801GLFT 数据手册

 浏览型号9DB801GLFT的Datasheet PDF文件第5页浏览型号9DB801GLFT的Datasheet PDF文件第6页浏览型号9DB801GLFT的Datasheet PDF文件第7页浏览型号9DB801GLFT的Datasheet PDF文件第9页浏览型号9DB801GLFT的Datasheet PDF文件第10页浏览型号9DB801GLFT的Datasheet PDF文件第11页 
Integrated  
Circuit  
ICS9DB801  
Systems, Inc.  
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair  
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9Ω, ΙREF = 475Ω  
PARAMETER  
Current Source Output  
Impedance  
SYMBOL  
Zo1  
CONDITIONS  
MIN  
TYP  
MAX  
850  
UNITS NOTES  
VO = Vx  
3000  
1
Statistical measurement on single  
ended signal using oscilloscope  
math function.  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
1,3  
1,3  
mV  
-150  
150  
Measurement on single ended  
signal using absolute value.  
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Vovs  
Vuds  
Vcross(abs)  
1150  
1
1
1
mV  
mV  
mV  
-300  
250  
550  
140  
Variation of crossing over all  
edges  
Crossing Voltage (var)  
d-Vcross  
1
Long Accuracy  
Rise Time  
Fall Time  
Rise Time Variation  
Fall Time Variation  
ppm  
tr  
tf  
d-tr  
d-tf  
see Tperiod min-max values  
VOL = 0.175V, VOH = 0.525V  
VOH = 0.525V VOL = 0.175V  
0
ppm  
ps  
ps  
ps  
ps  
1,2  
1
1
1
1
175  
175  
700  
700  
125  
125  
Measurement from differential  
wavefrom  
dt3  
Duty Cycle  
Skew  
45  
55  
50  
%
1
1
tsk3  
VT = 50%  
ps  
PLL mode,  
Measurement from differential  
wavefrom  
BYPASS mode as additive jitter  
50  
50  
ps  
ps  
1
1
tjcyc-cyc  
Jitter, Cycle to cycle  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock  
complies with CK409/CK410 accuracy requirements  
3IREF = VDD/(3xRR). For RR = 475(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.  
1015A—04/08/05  
8

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