Datasheet > 9DB801GLFT

9DB801GLFT

更新时间： 2024-02-19 16:05:28

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
18页	178K
描述
Clock Driver, PDSO48

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技术参数
数据手册

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9DB801GLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSSOP, TSSOP48,.3,20	Reach Compliance Code：	compliant
风险等级：	5.84	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e3	湿度敏感等级：	1
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP48,.3,20
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Clock Drivers	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
Base Number Matches：	1

9DB801GLFT 数据手册

Integrated

Circuit

ICS9DB801

Systems, Inc.

Pin Desription for OE_INV = 1

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

25 GND

PWR

Ground pin.

Asynchronous active high input pin used to power down the

device. The internal clocks are disabled and the VCO is stopped.

26 PD

27 SRC_STOP

28 HIGH_BW#

Active high input to stop SRC outputs.

3.3V input for selecting PLL Band Width

0 = High, 1= Low

29 DIF_4#

30 DIF_4

31 VDD

32 GND

33 DIF_5#

34 DIF_5

OUT

PWR

OUT

0.7V differential complement clock outputs

0.7V differential true clock outputs

Power supply, nominal 3.3V

Ground pin.

0.7V differential complement clock outputs

0.7V differential true clock outputs

Active low input for enabling DIF pair 5.

1 = tri-state outputs, 0 = enable outputs

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

0.7V differential complement clock outputs

0.7V differential true clock outputs

35 OE5#

36 OE6#

37 DIF_6#

38 DIF_6

39 VDD

OUT

PWR

Power supply, nominal 3.3V

This latched input selects the polarity of the OE pins.

0 = OE pins active high, 1 = OE pins active low (OE#)

0.7V differential complement clock outputs

0.7V differential true clock outputs

40 OE_INV

41 DIF_7#

42 DIF_7

OUT

Active low input for enabling DIF pair 4

1 = tri-state outputs, 0 = enable outputs

Active low input for enabling DIF pair 7.

1 = tri-state outputs, 0 = enable outputs

3.3V output indicating PLL Lock Status. This pin goes high when

43 OE4#

44 OE7#

45 LOCK

OUT

lock is achieved.

This pin establishes the reference current for the differential

current-mode output pairs. This pin requires a fixed precision

resistor tied to ground in order to establish the appropriate

current. 475 ohms is the standard value.

Ground pin for the PLL core.

46 IREF

47 GNDA

48 VDDA

PWR

3.3V power for the PLL core.

1015A—04/08/05

1 2 3 456 7 8...18

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