Datasheet > 935322088699

935322088699

更新时间： 2024-09-20 19:08:51

品牌	Logo	应用领域
恩智浦 - NXP		微控制器外围集成电路
页数	文件大小	规格书
168页	1586K
描述
RISC Microcontroller

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935322088699 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.67
uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC	Base Number Matches：	1

935322088699 数据手册

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5777M

Rev. 6, 06/2016

MPC5777M

416 TEPBGA

27mm x 27 mm

512 TEPBGA

MPC5777M Microcontroller

Data Sheet

25 mm x 25 mm

• Three main CPUs, single issue, 32-bit CPU core complexes

(e200z7), one of which is a dedicated lockstep core.

– Dual phase-locked loops with stable clock domain for

peripherals and FM modulation domain for

computational shell

– Power Architecture embedded specification

compliance

• Dual crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters with

end-to-end ECC

• Hardware Security Module (HSM) to provide robust

integrity checking of flash memory

• System Integration Unit Lite (SIUL)

• Boot Assist Module (BAM) supports factory programming

using serial bootload through ‘UART Serial Boot Mode

Protocol’. Physical interface (PHY) can be:

– UART/LIN

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– 16 KB Local instruction RAM and 64 KB local data

RAM

– 16 KB I-Cache and 4 KB D-Cache

• I/O Processor, dual issue, 32-bit CPU core complex

(e200z4), with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– Lightweight Signal Processing Auxiliary Processing

Unit (LSP APU) instruction support for digital signal

processing (DSP)

– CAN

• GTM104 — generic timer module

• Enhanced analog-to-digital converter system with

– Twelve separate 12-bit SAR analog converters

– Ten separate 16-bit Sigma-Delta analog converters

• Eight deserial serial peripheral interface (DSPI) modules

• Two Peripheral Sensor Interface (PSI5) controllers

• Three LIN and three UART communication interface

(LINFlexD) modules (6 total)

– 16 KB Local instruction RAM and 64 KB local data

RAM

– LINFlexD_0 is a Master/Slave

– 8 KB I-Cache

• 8640 KB on-chip flash

– LINFlexD_1, LINFlexD_2, LINFlexD_14,

LINFlexD_15, and LINFlexD_16 are Masters

• Four modular controller area network (MCAN) modules

and one time-triggered controller area network

(M-TTCAN)

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 404 KB on-chip general-purpose SRAM including 64 KB

standby RAM (+ 192 KB data RAM included in the

CPUs). Of this 404 KB, 64 KB can be powered by a

separate supply so the contents of this portion can be

preserved when the main MCU is powered down.

• Multichannel direct memory access controllers (eDMA): 2

x 64 channels per eDMA (128 channels total)

• Triple Interrupt controller (INTC)

• External Bus Interface (EBI)

– Dual routing of accesses to EBI

– Access path determined by access address

– Access path downstream of PFLASH controller

– Allows EBI accesses to share buffer and prefetch

capabilities of internal flash

– Allows internal flash accesses to be remapped to

memories connected to EBI

NXP reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

12 3 4 5 6 7...168

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