Document Number: MPC8360EEC
Rev. 5, 09/2011
Freescale Semiconductor
Technical Data
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications
Contents
This document provides an overview of the MPC8360E/58E
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . 12
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 25
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
18. HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
19. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
20. Package and Pin Listings . . . . . . . . . . . . . . . . . 63
21. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
22. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
23. System Design Information . . . . . . . . . . . . . . . 96
24. Ordering Information . . . . . . . . . . . . . . . . . . . . 99
25. Document Revision History . . . . . . . . . . . . . 100
PowerQUICC II Pro processor revision 2.x TBGA features, including a
block diagram showing the major functional components. This device is
a cost-effective, highly integrated communications processor that
addresses the needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include next generation
DSLAMs, network interface cards for 3G base stations (Node Bs),
routers, media gateways, and high end IADs. The device extends current
PowerQUICC II Pro offerings, adding higher CPU performance,
additional functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related to
time-to-market, price, power, and package size. This device can be used
for the control plane and also has data plane functionality.
For functional characteristics of the processor, refer to the MPC8360E
PowerQUICC II Pro Integrated Communications Processor Reference
Manual, Rev. 3.
To locate any updates for this document, refer to the MPC8360E product
summary page on our website listed on the back cover of this document
or contact your Freescale sales office.
1
Overview
This section describes a high-level overview including features and
general operation of the MPC8360E/58E PowerQUICC II Pro processor.
A major component of this device is the e300 core, which includes
32 Kbytes of instruction and data cache and is fully compatible with the
Power Architecture™ 603e instruction set. The new QUICC Engine
module provides termination, interworking, and switching between a
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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