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9248AG-92LF PDF预览

9248AG-92LF

更新时间： 2024-11-29 20:50:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
16页 369K
描述
Processor Specific Clock Generator, 100MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48

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9248AG-92LF 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48
针数：48Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.71其他特性：CAN ALSO OPERATE AT 3.3V SUPPLY
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：12.5 mm湿度敏感等级：1
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：100 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：2.625 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

9248AG-92LF 数据手册

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Integrated  
Circuit  
ICS9248-92  
Systems, Inc.  
TM  
Mobile Pentium II System Clock Chip  
RecommendedApplication:  
Features  
The ICS9248-92 is a fully compliant timing solution for the  
•
•
•
Generates system clocks for CPU, SDRAM, PCI, plus  
14.318MHz REF(0:2), USB, PlusSuperI/O  
I2C serial configuration interface provides output clock  
disabling and other functions  
Intel mobile 440BX/MX chipset requirements.  
GeneralDescription:  
FeaturesincludetwostrongCPU, sevenPCIandeightSDRAM  
clocks. Three reference outputs are available equal to the  
crystal frequency. Stronger drive CPUCLK outputs typically  
provide greater than 1 V/ns slew rate into 20pF loads. This  
device meets rise and fall requirements with 2 loads per CPU  
output (ie, one clock to CPU and NB chipset, one clock to two  
L2 cache inputs).  
MODE input pin selects optional power management  
input control pins  
•
•
•
•
•
•
•
Two fixed outputs separately selectable as 24 or 48MHz  
2.5Voutputs:CPU  
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz  
No power supply sequence requirements  
Usesexternal14.318MHzcrystal  
48pin240milTSSOPpackage  
PWR_DWN# pin allows low power mode by stopping crystal  
OSC and PLL stages. For optional power management,  
CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will  
stopPCICLK(0:5)clocks  
Output enable register  
for serial port control:  
1 = enable  
0 = disable  
PCICLK outputs typically provide better than 1V/ns slew rate  
into30pFloadswhilemaintaining50±5%dutycycle. TheREF  
clock outputs typically provide better than 0.5V/ns slew rates.  
The ICS9248-92 accepts a 14.318MHz reference crystal or  
clock as its input and runs on a 3.3V core supply.  
Pin Configuration  
Block Diagram  
48-Pin TSSOP 240 mil Package  
Functionality  
Crystal(X1, X2)=14.31818MHz  
SEL  
100/66#  
CPUCLK  
(MHz)  
PCICLK  
(MHz)  
0
66.6  
33.3  
1
100  
33.3  
Pentium is a trademark on Intel Corporation.  
9248-92RevE02/21/01  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
information being relied upon by the customer is current and accurate.  
1234567...16

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