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9248DF-39 PDF预览

9248DF-39

更新时间: 2024-11-29 20:11:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 321K
描述
Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48

9248DF-39 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.74JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
湿度敏感等级:1端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:150 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:2.5,3.3 V
主时钟/晶体标称频率:16 MHz认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Clock Generators
最大压摆率:180 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

9248DF-39 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-39  
Frequency Generator & Integrated Buffers for PENTIUM/ProTM  
General Description  
Features  
3.3V outputs: SDRAM, PCI, REF, 48/24MHz  
The ICS9248-39 generates all clocks required for high speed  
RISC or CISC microprocessor systems such as Intel  
PentiumPro or Cyrix. Eight different reference frequency  
multiplying factors are externally selectable with smooth  
frequency transitions.  
2.5V outputs: CPU, IOAPIC  
20 ohm CPU clock output impedance  
20 ohm PCI clock output impedance  
Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,  
center 2.6 ns.  
No external load cap for CL=18pF crystals  
±175 ps CPU clock skew  
Features include two CPU, six PCI and thirteen SDRAM  
clocks. Two reference outputs are available equal to the crystal  
frequency. Plus the IOAPIC output powered by VDDL1. One  
48 MHz for USB, and one 24 MHz clock for Super IO. Spread  
Spectrum built in at ±0.5% or ±0.25% modulation to reduce  
the EMI. Serial programming I2C interface allows changing  
functions, stop clock programing and Frequency selection.  
Additionally, the device meets the Pentium power-up  
stabilization, which requires that CPU and PCI clocks be  
stable within 2ms after power-up. It is not recommended to  
use I/O dual function pin for the slots (ISA, PIC, CPU,  
DIMM). The add on card might have a pull up or pull down.  
250ps (cycle to cycle) CPU jitter  
Smooth frequency switch, with selections from 66.8  
to 150 MHz CPU.  
I2C interface for programming  
3ms power up clock stable time  
Clock duty cycle 45-55%.  
48 pin 300 mil SSOP package  
3.3V operation, 5V tolerant inputs (with series R)  
<5ns propagation delay SDRAM from Buffer Input  
Pin Configuration  
High drive PCICLK and SDRAM outputs typically provide  
greater than 1 V/ns slew rate into 30pF loads. CPUCLK  
outputs typically provide better than 1V/ns slew rate into 20pF  
loads while maintaining 50±5% duty cycle. The REF and 24  
and 48 MHz clock outputs typically provide better than 0.5V/  
ns slew rates into 20pF.  
Block Diagram  
48-Pin SSOP  
* Internal Pull-up Resistor of 240K to VDD  
** Internal Pull-down resistor of 240K to GND  
Power Groups  
VDD1 = REF (0:1), X1, X2  
VDD2 = PCICLK_F, PCICLK(0:4)  
VDD3 = SDRAM (0:12), supply for PLL core  
VDD4 = 24MHz, 48MHz  
VDDL1 = IOAPIC  
VDDL2 = CPUCLK 1, CPUCLK_F  
Pentium is a trademark of Intel Corporation  
I2C is a trademark of Philips Corporation  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9248-39RevF12/16/99  
information being relied upon by the customer is current and accurate.  

9248DF-39 替代型号

型号 品牌 替代类型 描述 数据表
9248DF-39LF IDT

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SSOP-48, Tube
ICS9248DF-39LF IDT

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Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, GREEN, SSOP-48

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