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9248YF-185LFT PDF预览

9248YF-185LFT

更新时间: 2024-11-29 20:50:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
12页 128K
描述
Processor Specific Clock Generator, 133.33MHz, PDSO28, 0.209 INCH, ROHS COMPLIANT, SSOP-28

9248YF-185LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:10.2 mm端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:133.33 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:16 MHz认证状态:Not Qualified
座面最大高度:2 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

9248YF-185LFT 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9248-185  
Frequency Generator & Integrated Buffers for PENTIUM/ProTM  
& K6  
Pin Configuration  
RecommendedApplication:  
VIA PM133 chipset  
REF1/FREE_SEL*1  
VDDL  
CPUCLK0/_F  
CPUCLK1  
GND  
CLK_STOP#  
SDRAM0/_F  
SDRAM1  
SDRAM2  
GND  
VDDSDR  
SDRAM3  
SDRAM4  
VDD48  
OutputFeatures:  
VDD  
REF0  
GND  
1
2
3
4
5
6
8
9
10  
11  
12  
13  
14  
28  
2ꢀ  
26  
25  
24  
23  
22  
21  
20  
19  
18  
1ꢀ  
16  
15  
2 - CPUs @ 2.5V  
5 - SDRAM @ 3.3V  
3 - PCI @ 3.3V,  
1 - 48MHz, @ 3.3V fixed.  
2 - REF @ 3.3V, 14.318MHz.  
X1  
X2  
VDDPCI  
1*PCICLK_F  
GND  
1, 2FS1/PCICLK0  
Features:  
BUFFER_IN  
1PCICLK1  
PCI_STOP#  
GND  
Up to 133MHz frequency support  
Support power management:PCI_STOP &  
CLK_STOP  
*FS0/48MHz  
Spread spectrum for EMI control (-0.5% down  
spread).  
28-Pin SSOP/TSSOP  
Uses external 14.318MHz crystal  
FS pins for frequency select  
* Internal Pull-up Resistor of 120K to VDD  
1. These pin will have 2X drive strength  
2. FS1 is a pull down  
KeySpecifications:  
CPU – PCI Skew: 1-4ns  
PCI – PCI Skew: 500ps  
CPU – CPU Skew: 1ꢀ5ps  
CPU Jitter: 250ps (cyc-cyc)  
PCI Jitter: 500ps (cyc-cyc)  
Block Diagram  
Frequency Select  
Down  
Spread  
PLL2  
48MHz  
FS1  
FS0 CPUCLK PCICLK  
0
0
1
1
0
1
0
1
66.66  
100.00  
97.00  
33.33  
33.33  
32.33  
33.33  
-0.5%  
-0.5%  
-0.5%  
-0.5%  
X1  
X2  
XTAL  
OSC  
REF (1:0)  
CPUCLK1  
2
CPU  
DIVDER  
Stop  
Stop  
PLL1  
Spread  
Spectrum  
CPUCLK0/_F  
133.33  
BUFFER_IN  
SDRAM (4:1)  
SDRAM0/_F  
4
2
Control  
Logic  
PCI  
DIVDER  
PCI_STOP#  
CLK_STOP#  
FS (1:0)  
Stop  
PCICLK (1:0)  
PCICLK_F  
Config.  
Reg.  
Pentium is a trademark of Intel Corporation  
I2C is a trademark of Philips Corporation  
9248-185RevE- 12/15/08  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
information being relied upon by the customer is current and accurate.  

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