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9248BF-138LFT PDF预览

9248BF-138LFT

更新时间: 2024-11-29 20:53:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
14页 142K
描述
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, GREEN, MO-118, SSOP-48

9248BF-138LFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, GREEN, MO-118, SSOP-48
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.71JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
湿度敏感等级:1端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:166.67 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.8 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

9248BF-138LFT 数据手册

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ICS9248-138  
Integrated  
Circuit  
Systems, Inc.  
Frequency Generator & Integrated Buffers for Celeron & PII/III™  
Recommended Application:  
Pin Configuration  
810/810E and Solano type chipset.  
1*SEL24_48#/REF0  
VDDREF  
X1  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDLAPIC  
IOAPIC1  
Output Features:  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDDLCPU  
CPUCLK0  
CPUCLK1  
GNDLCPU  
GNDSDR  
SDRAM0  
SDRAM1  
SDRAM2  
VDDSDR  
SDRAM3  
SDRAM4  
SDRAM5  
GNDSDR  
SDRAM6  
SDRAM7  
SDRAM_F  
VDDSDR  
GND48  
2- CPUs @ 2.5V  
X2  
9 - SDRAM @ 3.3V, including 1 free running  
7 - PCICLK @ 3.3V  
GNDREF  
GND3V66  
3V66-0  
3V66-1  
3V66-2  
1 - IOAPIC @ 2.5V,  
3 - 3V66MHz @ 3.3V  
2 - 48MHz, @ 3.3V fixed.  
1 - 24/48MHz, @3.3V selectable by I2C  
1 - REF @v3.3V, 14.318MHz.  
VDD3V66  
VDDPCI  
1*FS0/PCICLK0  
1**FS1/PCICLK1  
GNDPCI  
PCICLK2  
PCICLK3  
PCICLK4  
VDDPCI  
PCICLK5  
PCICLK6  
GNDPCI  
PD#  
Features:  
Up to 200MHz frequency support  
Support FS0-FS4 strapping status bit for I2C read  
back.  
Support power management: Through Power down  
Mode from I2C programming.  
24_48MHz/FS2**  
48MHz/FS3*  
48MHz/FS4*1  
VDD48  
Spread spectrum for EMI control ( ± 0.25% center).  
Uses external 14.318MHz crystal  
SCLK  
SDATA  
Skew Specifications:  
CPU – CPU: <175ps  
48-Pin 300mil SSOP  
* These inputs have a 120K pull up to VDD.  
** These inputs have a 120K pull down to GND.  
1 These are double strength.  
SDRAM - SDRAM: < 250ps  
3V66 – 3V66: <175ps  
PCI – PCI: <500ps  
For group skew specifications, please refer to group  
timing relationship.  
Block Diagram  
Functionality  
CPU  
(MHz)  
66.67  
66.87  
68.67  
SDRAM  
(MHz)  
100.00  
100.30  
103.00  
107.00  
100.00  
100.30  
103.00  
107.00  
133.33  
133.73  
137.33  
120.00  
100.00  
100.30  
103.00  
90.00  
3V66  
(MHz)  
66.67  
66.87  
68.67  
71.34  
66.67  
66.87  
68.67  
71.34  
66.67  
66.87  
68.67  
60.00  
66.67  
66.87  
68.67  
60.00  
PCICLK  
(MHz)  
33.33  
33.43  
34.33  
35.66  
33.33  
33.43  
34.33  
35.66  
33.33  
33.43  
34.33  
30.00  
33.33  
33.43  
34.33  
30.00  
IOAPIC  
(MHz)  
16.67  
16.72  
17.16  
17.83  
16.67  
16.72  
17.17  
17.84  
16.67  
16.72  
17.17  
15.00  
16.67  
16.72  
17.17  
15.00  
FS4 FS3 FS2 FS1 FS0  
PLL2  
48MHz [1:0]  
24_48MHz  
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
/ 2  
X1  
X2  
XTAL  
OSC  
REF0  
71.34  
100.00  
100.30  
103.00  
107.00  
133.33  
133.73  
137.33  
120.00  
133.33  
133.73  
137.33  
120.00  
PLL1  
Spread  
Spectrum  
CPU  
DIVDER  
CPUCLK [1:0]  
2
8
SDRAM  
DIVDER  
SDRAM [7:0]  
SDRAM_F  
IOAPIC  
SEL24_48#  
IOAPIC  
DIVDER  
Control  
Logic  
SDATA  
SCLK  
PCI  
DIVDER  
PCICLK [6:0]  
3V66 [2:0]  
7
FS[4:0]  
PD#  
Config.  
Reg.  
3V66  
DIVDER  
3
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00  
160.00  
166.67  
166.67  
160.00  
120.00  
166.67  
125.00  
80.00  
80.00  
83.34  
83.34  
40.00  
40.00  
41.67  
41.67  
20.00  
20.00  
20.84  
20.84  
AdditionalfrequenciesselectablethroughI2Cprogramming.  
0342C—08/26/03  

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