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844003AKI-02T

更新时间： 2024-09-17 14:47:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
16页 320K
描述
Clock Generator, 700MHz, 5 X 5 MM, 0.75 MM HEIGHT, MO-220, VFQFN-32

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844003AKI-02T 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：32
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.32
Is Samacsys：NJESD-30 代码：S-XQCC-N32
JESD-609代码：e0长度：5 mm
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：700 MHz
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：225主时钟/晶体标称频率：25 MHz
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压：3.63 V最小供电电压：2.97 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

844003AKI-02T 数据手册

 浏览型号844003AKI-02T的Datasheet PDF文件第1页浏览型号844003AKI-02T的Datasheet PDF文件第3页浏览型号844003AKI-02T的Datasheet PDF文件第4页浏览型号844003AKI-02T的Datasheet PDF文件第5页浏览型号844003AKI-02T的Datasheet PDF文件第6页浏览型号844003AKI-02T的Datasheet PDF文件第7页 
ICS844003I-02  
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
Type  
Description  
1, 7, 13,  
22  
GND  
Power  
Input  
Power supply ground.  
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the  
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal  
circuit with a single-ended reference clock.  
2,  
3
XTAL_IN,  
XTAL_OUT  
Crystal select pin. Selects between the single-ended REF_CLK or crystal  
interface. Has an internal pullup resistor so the crystal interface is selected  
by default. LVCMOS/LVTTL interface levels.  
VCO select pin. When Low, the PLL is bypassed and the crystal reference  
or REF_CLK (depending on XTAL_SEL setting) are passed directly to the  
output dividers. Has an internal pullup resistor so the PLL is not bypassed  
by default. LVCMOS/LVTTL interface levels.  
4
5
XTAL_SEL  
VCO_SEL  
Input  
Input  
Pullup  
Pullup  
Active HIGH Master Reset. When logic HIGH, the internal dividers are  
reset, (except for ÷1 state, when the device is configured as a buffer),  
causing the true outputs QXx to go low and the inverted outputs nQXx to  
6
MR  
Input  
Pulldown go high. When logic LOW, the internal dividers and the outputs are  
enabled. MR has an internal pulldown resistor so the power-up default  
state of outputs and dividers are enabled.  
LVCMOS/LVTTL interface levels.  
8, 26,  
29, 30  
nc  
Unused  
Input  
No connect.  
Division select pin for Bank A. Default = LOW.  
Pulldown  
9
DIV_SELA1  
DIV_SELA0  
DIV_SELB1  
DIV_SELB0  
LVCMOS/LVTTL interface levels.  
Division select pin for Bank A. Default = HIGH.  
LVCMOS/LVTTL interface levels.  
Division select pin for Bank B. Default = LOW.  
LVCMOS/LVTTL interface levels.  
Division select pin for Bank B. Default = HIGH.  
LVCMOS/LVTTL interface levels.  
10  
11  
12  
Input  
Pullup  
Input  
Pulldown  
Input  
Pullup  
Feedback divide select. When Low (default), the feedback divider is set  
Pulldown for ÷20. When HIGH, the feedback divider is set for ÷24.  
LVCMOS/LVTTL interface levels.  
14  
15  
FB_DIV  
OEB  
Input  
Input  
Output enable Bank B. Active High output enable. When logic HIGH, the  
output pair on Bank B is enabled. When logic LOW, the output pair drives  
Pullup  
Pullup  
differential Low (QBx = Low, nQBx = High). Has an internal pullup resistor  
so the default power-up state of outputs are enabled.  
LVCMOS/LVTTL interface levels.  
Output enable Bank A. Active High output enable. When logic HIGH, the  
2 output pairs on Bank A are enabled. When logic LOW, the output pair  
drives differential Low (QA0 = Low, nQA0 = High). Has an internal pullup  
resistor so the default power-up state of outputs are enabled.  
LVCMOS/LVTTL interface levels.  
16  
OEA  
Input  
17  
VDDO_B  
Power  
Output supply pin for Bank B outputs.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Differential output pair. LVDS interface levels.  
Output supply pin for Bank A outputs.  
Core supply pins.  
18, 19  
20, 21  
23, 24  
25  
nQB1, QB1 Output  
nQB0, QB0  
nQA0, QA0  
VDDO_A  
Output  
Ouput  
Power  
Power  
Power  
27, 31  
28  
VDD  
VDDA  
Analog supply pin.  
Single-ended reference clock input. Has an internal pulldown resistor to  
32  
REF_CLK  
Input  
Pulldown pull to low state by default. Can leave floating if using the crystal interface.  
LVCMOS/LVTTL interface levels.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER  
2
ICS844003AKI-02 REV. A FEBRUARY 22, 2007  
1234567...16

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