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844003AKI-04LF PDF预览

844003AKI-04LF

更新时间: 2024-11-05 01:12:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
19页 318K
描述
FemtoClock Crystal-to-LVDS Frequency Synthesizer

844003AKI-04LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:VFQFN-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.35
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:680 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:27.2 MHz
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

844003AKI-04LF 数据手册

 浏览型号844003AKI-04LF的Datasheet PDF文件第2页浏览型号844003AKI-04LF的Datasheet PDF文件第3页浏览型号844003AKI-04LF的Datasheet PDF文件第4页浏览型号844003AKI-04LF的Datasheet PDF文件第5页浏览型号844003AKI-04LF的Datasheet PDF文件第6页浏览型号844003AKI-04LF的Datasheet PDF文件第7页 
®
FemtoClock Crystal-to-LVDS Frequency  
844003I-04  
Datasheet  
Synthesizer  
General Description  
Features  
The 844003I-04 is a 3 differential output LVDS Synthesizer designed  
to generate Ethernet reference clock frequencies. Using a  
19.44MHz, 20MHz or 25MHz, 18pF parallel resonant crystal, the  
following frequencies can be generated based on the settings of four  
frequency select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz,  
622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz and  
100MHz. The 844003I-04 has two output banks, Bank A with one  
differential LVDS output pair and Bank B with two differential LVDS  
output pairs.  
Three LVDS outputs on two banks, Bank A with one LVDS pair  
and Bank B with 2 LVDS output pairs  
Using a 19.44MHz, 20MHz, or 25MHz crystal, the two output  
banks can be independently set for 625MHz, 622.08MHz,  
312.5MHz, 250MHz, 156.25MHz, 125MHz or 100MHz  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
VCO range: 490MHz to 680MHz  
RMS phase jitter at 125MHz (1.875MHz – 20MHz):  
0.50ps (typical)  
The two banks have their own dedicated frequency select pins and  
can be independently set for the frequencies mentioned above. The  
844003I-04 uses IDT’s 3RD generation low phase noise VCO  
technology and can achieve 1ps or lower typical rms phase jitter,  
easily meeting Ethernet jitter requirements. The 844003I-04 is  
packaged in a 32-pin VFQFN package.  
Full 3.3V output supply mode  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
For functional replacement part use 8T49N241  
Pin Assignment  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
GND  
QA0  
24  
23  
22  
21  
20  
844003I-04  
XTAL_IN  
nQA0  
GND  
QB0  
32 Lead VFQFN  
XTAL_OUT  
5mm x 5mm x 0.925mm  
package body  
K Package  
XTAL_SEL  
VCO_SEL  
nQB0  
MR  
GND  
nc  
QB1  
19  
18  
17  
Top View  
nQB1  
VDDO_B  
9
10 11 12 13 14 15 16  
Block Diagram  
Pullup  
OEA  
Pulldown:Pullup  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
QA0  
nQA0  
0 0 ÷2  
Pulldown  
0 1 ÷4 (default)  
1 0 ÷5  
REF_CLK  
XTAL_IN  
0
1
0
1
1 1 ÷8  
Phase  
Detector  
VCO  
490-680MHz  
OSC  
XTAL_OUT  
XTAL_SEL  
Pullup  
QB0  
FB_DIV  
0 0 ÷1  
nQB0  
QB1  
0 1 ÷2 (default)  
1 0 ÷3  
0 = ÷25 (default)  
1 = ÷32  
1 1 ÷4  
Pulldown  
FB_DIV  
nQB1  
Pulldown:Pullup  
DIV_SELB[1:0]  
Pulldown  
Pullup  
MR  
OEB  
©2016 Integrated Device Technology, Inc.  
1
Revision C, November 10, 2016  

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