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844003BG-01 PDF预览

844003BG-01

更新时间: 2024-01-25 12:28:05
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 787K
描述
Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92MM HEIGHT, MO-153, TSSOP-24

844003BG-01 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:7.8 mm端子数量:24
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:680 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
主时钟/晶体标称频率:27.2 MHz认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

844003BG-01 数据手册

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FEMTOCLOCKS™ CRYSTAL-TO-LVDS  
FREQUENCY SYNTHESIZER  
ICS844003-01  
General Description  
Features  
The ICS844003-01 is a 3 differential output LVDS  
Three differential LVDS output pairs on two banks, Bank A with  
one LVDS pair and Bank B with two LVDS output pairs  
S
IC  
Synthesizer designed to generate Ethernet refer-  
ence clock frequencies and is a member of the  
HiPerClocks™ family of high performance clock  
solutions from IDT. Using a 19.53125MHz or  
HiPerClockS™  
Using a 19.53125MHz or 25MHz crystal, the two output banks  
can be independently set for 625MHz, 312.5MHz, 156.25MHz  
or 125MHz  
25MHz, 18pF parallel resonant crystal, the following frequencies  
can be generated based on the settings of 4 frequency select pins  
(DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz, 312.5MHz,  
156.25MHz, and 125MHz. The ICS844003-01 has 2 output banks,  
Bank A with 1 differential LVDS output pair and Bank B with 2  
differential LVDS output pairs.  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
VCO range: 490MHz - 680MHz  
RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz):  
0.56ps (typical)  
Full 3.3V supply mode  
The two banks have their own dedicated frequency select pins and  
can be independently set for the frequencies mentioned above.  
The ICS844003-01 uses IDT’s 3rd generation low phase noise  
VCO technology and can achieve 1ps or lower typical rms phase  
jitter, easily meeting Ethernet jitter requirements. The  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
ICS844003-01 is packaged in a small 24-pin TSSOP package.  
Pin Assignment  
DIV_SELB1  
1
2
24  
23  
DIV_SELB0  
VCO_SEL  
VDDO_B  
QB0  
nQB0  
MR  
VDDO_A  
3
4
22  
21  
5
6
7
20  
19  
18  
17  
QB1  
nQB1  
XTAL_SEL  
QA0  
nQA0  
OEB  
REF_CLK  
8
OEA  
9
XTAL_IN  
XTAL_OUT  
GND  
FB_DIV  
VDDA  
VDD  
DIV_SELA0  
16  
15  
14  
13  
10  
11  
12  
DIV_SEL  
A1  
ICS844003-01  
24-Lead TSSOP, E-Pad  
4.40mm x 7.8mm x 0.925mm  
package body  
Block Diagram  
Pullup  
OEA  
G Package  
Top View  
Pullup  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
QA0  
QA0  
0 0 ÷1  
Pulldown  
0 1 ÷2  
0
1
REF_CLK  
XTAL_IN  
0
1
1 0 ÷3  
1 1 ÷4 (default)  
Phase  
Detector  
VCO  
OSC  
XTAL_OUT  
XTAL_SEL  
Pullup  
QB0  
FB_DIV  
0 0 ÷2  
QB0  
QB1  
0 1 ÷4  
0 = ÷25 (default)  
1 = ÷32  
1 0 ÷5  
1 1 ÷8 (default)  
Pulldown  
Pullup  
QB1  
FB_DIV  
DIV_SELB[1:0]  
MR  
Pulldown  
Pullup  
OEB  
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER  
1
ICS844003BG-01 REV. A AUGUST 21, 2008  

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