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844008AYI-15T PDF预览

844008AYI-15T

更新时间: 2024-11-04 20:59:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
13页 832K
描述
PLL/Frequency Synthesis Circuit

844008AYI-15T 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:not_compliant风险等级:5.8
JESD-609代码:e0湿度敏感等级:3
端子面层:Tin/Lead (Sn85Pb15)Base Number Matches:1

844008AYI-15T 数据手册

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PRELIMINARY  
ICS844008I-15  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ C RYSTAL-TO-  
LVDS FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS844008I-15 is an 8 output LVDS • Eight LVDS outputs  
ICS  
HiPerClockS™  
Synthesizer optimized to generate PCI Express  
• Crystal oscillator interface  
reference clock frequencies and is a member  
• Supports the following output frequencies:  
100MHz or 125MHz  
of the HiPerClocksTM family of high performance  
clock solutions from ICS. Using a 25MHz  
• VCO: 500MHz  
parallel resonant crystal, the following frequencies can be  
generated based on F_SEL pin: 100MHz or 125MHz. The  
ICS844008I-15 uses ICS’ 3rd generation low phase noise  
VCO technology and can achieve <1ps typical rms phase  
jitter, easily meeting PCI Express jitter requirements. The  
ICS844008I-15 is packaged in a 32-pin LQFP package.  
• RMS phase jitter @ 125MHz, using a 25MHz crystal  
(1.875MHz - 20MHz): 0.42ps (typical)  
• Full 3.3V supply modes  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and lead-free RoHS compliant  
packages  
FREQUENCY SELECT FUNCTIONTABLE  
Input  
Input  
Output  
Frequency  
(MHz)  
M Divider N Divider M/N Divider Frequency  
F_SEL  
Value  
Value  
Value  
(MHz)  
25MHz  
0
20  
4
5
125  
25MHz  
1
20  
5
4
100  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Pullup  
OE1  
Q0  
Pulldown  
nPLL_SEL  
nQ0  
32 31 30 29 28 27 26 25  
Q1  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
Q0  
nQ0  
VDD  
Q1  
Q7  
1
0
nQ1  
Q2  
nQ7  
VDD  
Q6  
25MHz  
ICS844008I-15  
32-Lead LQFP  
7mm x 7mm x 1.4mm  
package body  
Y Package  
VCO  
500MHz  
(w/25MHz  
Reference)  
XTAL_IN  
Phase  
Detector  
÷4  
÷5  
OSC  
nQ2  
Q3  
nQ1  
GND  
Q2  
nQ6  
GND  
Q5  
XTAL_OUT  
nQ3  
Q4  
Top View  
M = ÷20 (fixed)  
nQ2  
nQ5  
9
10 11 12 13 14 15 16  
nQ4  
Q5  
nQ5  
Q6  
nQ6  
Q7  
nQ7  
Pulldown  
MR  
Pullup  
F_SEL  
Pullup  
OE2  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on  
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications  
without notice.  
844008AYI-15  
www.icst.com/products/hiperclocks.html  
REV.B APRIL 28, 2006  
1

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