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8440259DK-05LF PDF预览

8440259DK-05LF

更新时间: 2024-11-05 01:12:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
16页 258K
描述
FemtoClock NG Crystal/LVCMOS-to-LVDS/LVCMOS Frequency Synthesizer

8440259DK-05LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:VFQFN-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:32最高工作温度:70 °C
最低工作温度:最大输出时钟频率:125 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:25 MHz
座面最大高度:1 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

8440259DK-05LF 数据手册

 浏览型号8440259DK-05LF的Datasheet PDF文件第2页浏览型号8440259DK-05LF的Datasheet PDF文件第3页浏览型号8440259DK-05LF的Datasheet PDF文件第4页浏览型号8440259DK-05LF的Datasheet PDF文件第5页浏览型号8440259DK-05LF的Datasheet PDF文件第6页浏览型号8440259DK-05LF的Datasheet PDF文件第7页 
FemtoClock® NG Crystal/LVCMOS-to-  
LVDS/LVCMOS Frequency Synthesizer  
8440259D-05  
DATASHEET  
GENERAL DESCRIPTION  
FEATURES  
Five differential LVDS outputs at 125MHz  
Three LVCMOS/LVTTL single-ended outputs at 125MHz  
One LVCMOS/LVTTL single-ended output at 3.90625MHz  
The ICS8440259D-05 is a 9 output synthesizer optimized to  
generate Gigabit and 10 Gigabit Ether-net. Using a 25MHz, 18pF  
parallel resonant crystal, the device will generate 125MHz and  
3.90625MHz clocks with mix-ed LVDS and LVCMOS/LVTTL output  
levels. The ICS8440259D-05 uses IDT’s 3rd generations low phase  
noiseVCO technology and can achieve <1ps typical rms phase jitter,  
easily meeting Ethernet jitter requirements. The ICS8440259D-05  
is packaged in a small, 32-pin VFQFN package that is optimum for  
applications with space limitations.  
Selectable crystal oscillator interface or LVCMOS/LVTTL sin-  
gle-ended input and PLL bypass from a single select pin  
VCO range: 510MHz - 650MHz  
RMS phase jitter @ 125MHz, using a 25MHz crystal  
(1.875MHz - 20MHz): 0.41ps (typical)  
Full 3.3V supply mode  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
BLOCK DIAGRAM  
Pullup  
nPLL_BYPASS  
Q0  
0
1
Pulldown  
REF_CLK  
0
nQ0  
25MHz  
VCO  
Phase  
Detector  
÷5  
XTAL_IN  
1
OSC  
Q1  
XTAL_OUT  
nQ1  
PIN ASSIGNMENT  
Q2  
÷25  
nQ2  
Q3  
nQ3  
Q4  
32 31 30 29 28 27 26 25  
24  
23  
22  
21  
20  
19  
18  
Q0  
nQ0  
Q8  
1
2
3
4
5
6
7
nQ4  
Q5  
VDDO_LVCMOS  
ICS8440259D-05  
32-Lead VFQFN  
5mm x 5mm x 0.925mm  
package body  
Q7  
GND  
Q1  
GND  
nQ1  
Q6  
VDDO_LVDS  
VDDO_LVCMOS  
Q6  
Q7  
K Package  
Top View  
Q2  
Q5  
GND  
nQ2  
8
17  
9
10 11 12 13 14 15 16  
Q8  
÷32  
8440259D-05 REVISION A SEPTEMBER 3, 2014  
1
©2014 Integrated Device Technology, Inc.  

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