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844003AGLFT PDF预览

844003AGLFT

更新时间: 2024-11-05 01:14:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 338K
描述
FemtoClock Crystal-to-3.3V LVDS Frequency Synthesizer

844003AGLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:7.8 mm湿度敏感等级:1
端子数量:24最高工作温度:70 °C
最低工作温度:最大输出时钟频率:700 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:35 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

844003AGLFT 数据手册

 浏览型号844003AGLFT的Datasheet PDF文件第2页浏览型号844003AGLFT的Datasheet PDF文件第3页浏览型号844003AGLFT的Datasheet PDF文件第4页浏览型号844003AGLFT的Datasheet PDF文件第5页浏览型号844003AGLFT的Datasheet PDF文件第6页浏览型号844003AGLFT的Datasheet PDF文件第7页 
®
FemtoClock Crystal-to-3.3V LVDS  
844003  
Datasheet  
Frequency Synthesizer  
General Description  
Features  
The 844003 is a three differential output LVDS Synthesizer designed  
to generate Ethernet reference clock frequencies. Using a 31.25MHz  
or 26.041666MHz, 18pF parallel resonant crystal, the following  
frequencies can be generated based on the settings of four  
frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,  
312.5MHz, 156.25MHz, and 125MHz. The 844003 has two output  
banks, Bank A with one differential LVDS output pair and  
Bank B with two differential LVDS output pairs.  
Three LVDS outputs on two banks, A Bank with one LVDS pair  
and B Bank with two LVDS output pairs  
Using a 31.25MHz or 26.041666MHz crystal, the two output  
banks can be independently set for 625MHz, 312.5MHz,  
156.25MHz or 125MHz  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended input  
VCO range: 560MHz to 700MHz  
The two banks have their own dedicated frequency select pins and  
can be independently set for the frequencies mentioned above. The  
844003 uses IDT’s 3rd generation low phase noise VCO technology  
and can achieve 1ps or lower typical rms phase jitter, easily meeting  
Ethernet jitter requirements. The 844003 is packaged in a small  
24-pin TSSOP package.  
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.63ps (typical)  
3.3V output supply mode  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) packaging  
Pin Assignment  
DIV_SELB0  
VCO_SEL  
1
2
24 DIV_SELB1  
23 VDDO_B  
MR  
VDDO_A  
QA0  
nQA0  
OEB  
OEA  
FB_DIV  
VDDA 10  
VDD 11  
3
4
5
6
7
8
9
22 QB0  
21 nQB0  
20 QB1  
19 nQB1  
18 XTAL_SEL  
17 TEST_CLK  
16 XTAL_IN  
15 XTAL_OUT  
14 GND  
Block Diagram  
DIV_SELA0 12  
13 DIV_SELA1  
844003  
24-Lead TSSOP  
Pullup  
OEA  
4.40mm x 7.8mm x 0.92mm  
package body  
Pulldown:Pullup  
DIV_SELA[1:0]  
Pullup  
VCO_SEL  
G Package  
Top View  
QA0  
0 0 ÷1  
Pulldown  
0 1 ÷2 (default)  
1 0 ÷4  
nQA0  
0
TEST_CLK  
0
1 1 ÷5  
XTAL_IN  
Phase  
Detector  
1
OSC  
1
VCO  
XTAL_OUT  
Pullup  
QB0  
XTAL_SEL  
FB_DIV  
0 0 ÷1  
nQB0  
QB1  
0 1 ÷2  
0 = ÷20 (default)  
1 0 ÷4 (default)  
1 1 ÷5  
1 = ÷24  
Pulldown  
nQB1  
FB_DIV  
DIV_SELB[1:0]  
MR  
Pullup:Pulldown  
Pulldown  
Pullup  
OEB  
©2016 Integrated Device Technology, Inc.  
1
January 29, 2016  

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