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8432CY-111 PDF预览

8432CY-111

更新时间: 2024-11-04 09:41:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 148K
描述
PLL Based Clock Driver, 8432 Series, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

8432CY-111 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.27
系列:8432输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:2最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.06 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

8432CY-111 数据手册

 浏览型号8432CY-111的Datasheet PDF文件第2页浏览型号8432CY-111的Datasheet PDF文件第3页浏览型号8432CY-111的Datasheet PDF文件第4页浏览型号8432CY-111的Datasheet PDF文件第5页浏览型号8432CY-111的Datasheet PDF文件第6页浏览型号8432CY-111的Datasheet PDF文件第7页 
ICS8432-111  
700MHZ/350MHZ  
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8432-111 is a general purpose, dual output  
Differential-to-3.3V LVPECL High Frequency Synthesizer.  
The ICS8432-111 has a selectable differential CLK, nCLK  
pair or LVCMOS/LVTTL TEST_CLK. The TEST_CLK input  
accepts LVCMOS or LVTTL input levels and translates them  
to 3.3V LVPECL levels. The CLK, nCLK pair can accept most  
standard differential input levels.The VCO operates at a  
frequency range of 200MHz to 700MHz. The VCO frequency  
is programmed in steps equal to the value of the input differ-  
ential or single ended reference frequency. Output frequen-  
cies up to 700MHz for FOUT and 350MHz for FOUT/2 can be  
programmed using the serial or parallel interfaces to the con-  
figuration logic. The low phase noise characteristics and the  
multiple frequency outputs of the ICS8432-111 makes it an  
ideal clock source for Fibre Channel 1 and 2, and Infiniband  
applications.  
Dual differential 3.3V LVPECL outputs  
Selectable differential CLK, nCLK pair or LVCMOSTEST_CLK  
CLK, nCLK pair can accept the following differential input  
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
TEST_CLK can accept the following input types:  
LVCMOS or LVTTL  
Maximum FOUT frequency: 700MHz  
Maximum FOUT/2 frequency: 350MHz  
CLK, nCLK or TEST_CLK input frequency: 40MHz  
VCO range: 250MHz to 700MHz  
Parallel or serial interface for programming counter  
andVCO frequency multiplier and dividers  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 40ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free  
(RoHS 6) packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
CLK_SEL  
TEST_CLK  
0
1
32 31 30 29 28 27 26 25  
CLK  
nCLK  
M5  
M6  
M7  
M8  
N0  
N1  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CLK  
TEST_CLK  
CLK_SEL  
VCCA  
ICS8432-111  
10 11 12 13 14 15 16  
32-Lead LQFP  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
÷1  
÷2  
÷4  
÷8  
MR  
0
1
VEE  
VCO  
FOUT  
nFOUT  
FOUT/2  
nFOUT/2  
9
÷M  
÷2  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N1  
Y Package  
TopView  
8432CY-111  
www.idt.com  
REV. C OCTOBER 5, 2010  
1

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