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84330CI PDF预览

84330CI

更新时间: 2024-11-05 01:04:55
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 360K
描述
720MHz, Low Jitter, Crystal-to-LVPECL Frequency Synthesizer

84330CI 数据手册

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720MHz, Low Jitter, Crystal-to-LVPECL  
Frequency Synthesizer  
84330CI  
Data Sheet  
General Description  
Features  
The 84330CI is a general purpose, single output high frequency  
synthesizer. The VCO operates at a frequency range of 250MHz to  
720MHz. The VCO and output frequency can be programmed using  
the serial or parallel interfaces to the configuration logic. The output  
can be configured to divide the VCO frequency by 1, 2, 4, and 8.  
Output frequency steps as small as 250kHz to 2MHz can be  
achieved using a 16MHz crystal depending on the output divider  
settings.  
Fully integrated PLL, no external loop filter requirements  
One differential 3.3V LVPECL output  
Crystal oscillator interface: 10MHz to 25MHz  
Output frequency range: 31.25MHz to 720MHz  
VCO range: 250MHz to 720MHz  
Parallel or serial interface for programming M and N dividers  
during power-up  
RMS period jitter: 6ps (maximum)  
Cycle-to-cycle jitter: 40ps (maximum)  
3.3V supply voltage  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) packages  
Pin Assignments  
25 24 23 22 21 20 19  
26  
27  
28  
1
N1  
S_CLOCK  
18  
17  
16  
15  
N0  
M8  
M7  
M6  
S_DATA  
S_LOAD  
ICS84330CI  
28 Lead PLCC  
V Package  
VCCA  
11.6mm x 11.4mm x 4.1mm  
FREF_EXT  
14  
13  
2
3
4
package body  
Top View  
Block Diagram  
XTAL_SEL  
XTAL1  
M5  
M4  
12  
Pullup  
OE  
5
6
7
8
9
10 11  
XTAL1  
1
0
OSC  
XTAL2  
Pulldown  
FREF_EXT  
÷16  
Pullup  
XTAL_SEL  
32 31 30 29 28 27 26 25  
PLL  
1
S_CLOCK  
nc  
24  
23  
22  
21  
20  
÷2  
÷4  
÷8  
÷1  
PHASEDETECTOR  
÷M  
2
3
4
5
6
7
8
S_DATA  
S_LOAD  
N1  
N0  
M8  
M7  
ICS84330CI  
32 Lead LQFP  
Y Package  
1
0
FOUT  
nFOUT  
VCO  
÷2  
VCCA  
VCCA  
7mm x 7mm x 1.4mm  
package body  
Top View  
FREF_EXT  
XTAL_SEL  
XTAL1  
M6  
M5  
M4  
19  
18  
17  
Pulldown  
Pulldown  
Pulldown  
Pullup  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
9
10 11 12 13 14 15 16  
Pullup  
Pullup  
M0:M8  
N0:N1  
©2016 Integrated Device Technology, Inc  
1
Revision A January 13, 2016  

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