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8433625AGLFT PDF预览

8433625AGLFT

更新时间: 2024-11-05 01:12:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 412K
描述
FemtoClock Crystal-to-3.3V LVPECL Frequency Synthesizer

8433625AGLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
JESD-30 代码:R-PDSO-G24JESD-609代码:e3
长度:7.8 mm湿度敏感等级:1
端子数量:24最高工作温度:70 °C
最低工作温度:最大输出时钟频率:625 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:26.0416 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:125 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

8433625AGLFT 数据手册

 浏览型号8433625AGLFT的Datasheet PDF文件第2页浏览型号8433625AGLFT的Datasheet PDF文件第3页浏览型号8433625AGLFT的Datasheet PDF文件第4页浏览型号8433625AGLFT的Datasheet PDF文件第5页浏览型号8433625AGLFT的Datasheet PDF文件第6页浏览型号8433625AGLFT的Datasheet PDF文件第7页 
®
FemtoClock Crystal-to-3.3V LVPECL  
8433625  
Datasheet  
Frequency Synthesizer  
General Description  
Features  
The 8433625 is a 3 differential output LVPECL Synthesizer designed  
to generate Ethernet reference clock frequencies. Using a 25MHz or  
26.041666MHz, 18pF parallel resonant crystal, the following  
frequencies can be generated based on the settings of 4 frequency  
select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz, 312.5MHz,  
156.25MHz, and 125MHz. The 8433625 has 2 output banks, Bank A  
with 1 differential LVPECL output pair and Bank B with 2 differential  
LVPECL output pairs.  
Three 3.3V LVPECL outputs on two banks, A Bank with one  
LVPECL pair and B Bank with 2 LVPECL output pairs  
Using a 25MHz or 26.041666 crystal, the two output banks can be  
independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz  
Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
VCO range: 520MHz – 680MHz  
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):  
The two banks have their own dedicated frequency select pins and  
can be independently set for the frequencies mentioned above. The  
8433625 uses IDT’s 3rd generation low phase noise VCO technology  
and can achieve 1ps or lower typical rms phase jitter, easily meeting  
Ethernet jitter requirements. The 8433625 is packaged in a small  
24-pin TSSOP package.  
0.3ps (typical)  
Full 3.3V supply mode  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Pin Assignment  
24  
23  
22  
21  
1
2
3
4
SELB  
1
VCCO_B  
QB  
nQB0  
QB  
DIV_SELB0  
VCO_SEL  
DIV_  
MR  
VCCO_A  
0
20  
19  
18  
17  
QA  
nQA  
OEB  
OEA  
5
6
7
1
nQB  
1
XTAL _SEL  
_
8
F
RE CL  
K
9
10  
11  
16  
15  
14  
13  
XTAL _IN  
XTAL _OUT  
VEE  
FB_DIV  
VCCA  
VCC  
DIV SELA0 12  
_
DIV_SE  
LA1  
8433625  
24-Lead TSSOP  
4.4mm x 7.8mm x 0.925mm package body  
G Package  
Top View  
©2016 Integrated Device Technology, Inc.  
1
Revision B, February 2, 2016  

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