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84330CM-01 PDF预览

84330CM-01

更新时间: 2024-11-04 21:19:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 1473K
描述
Clock Generator, 700MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MS-119, SOIC-28

84330CM-01 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MS-119, SOIC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.85JESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:18.05 mm
湿度敏感等级:1端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:700 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225电源:3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

84330CM-01 数据手册

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700MHz, Low Jitter, Crystal-To-3.3V LVPECL ICS84330-01  
Frequency Synthesizer  
General Description  
Features  
The ICS84330-01 is a general purpose, single output  
high frequency synthesize. The VCO operates at a  
frequency range of 250MHz to 700MHz. The VCO and  
output frequency can be programmed using the serial  
or parallel interfaces to the configuration logic. The  
Fully integrated PLL, no external loop filter requirements  
One differential 3.3V LVPECL output  
S
IC  
HiPerClockS™  
Crystal oscillator interface: 10MHz – 25MHz  
Output frequency range: 31.25MHz – 700MHz  
VCO range: 250MHz – 700MHz  
output can be configured to divide the VCO frequency by 1, 2, 4, and  
8. Output frequency steps from 250kHz to 2MHz can be achieved  
using a 16MHz crystal depending on the output divider setting.  
Parallel or serial interface for programming M and N dividers  
during power-up  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 40ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
Pin Assignments  
M0  
M1  
1
2
28 nP_LOAD  
27  
VCC  
M2  
M3  
3
4
26 XTAL_OUT  
25 XTAL_IN  
XTAL_IN  
OSC  
M4  
M5  
M6  
M7  
M8  
N0  
N1  
VEE  
TEST  
nc  
nc  
VCCA  
S_LOAD  
S_DATA  
S_CLOCK  
VCCO  
FOUT  
nFOUT  
VEE  
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
XTAL_OUT  
9
÷16  
10  
11  
12  
13  
PLL  
PHASEDETECTOR  
÷M  
÷1  
÷2  
÷4  
÷8  
VCC 14  
1
0
FOUT  
nFOUT  
ICS84330-01  
VCO  
÷2  
28 Lead SOIC  
7.5mm x 18.05mm x 2.25mm package body  
M Package  
Top View  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
M0:M8  
N0:N1  
25 24 23 22 21 20 19  
26  
27  
28  
1
N1  
17 N0  
S_CLOCK  
18  
ICS84330-01  
28 Lead PLCC  
11.5mm x 11.5mm x 4.4mm  
package body  
S_DATA  
S_LOAD  
M8  
M7  
M6  
16  
15  
14  
13  
VCCA  
nc  
V Package  
Top View  
2
nc  
M5  
M4  
3
XTAL_IN  
4
12  
5
6
7
8
9
10 11  
ICS84330CM-01 REVISION A FEBRUARY 23, 2010  
1
©2010 Integrated Device Technology, Inc.  

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