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8432CY-51LF PDF预览

8432CY-51LF

更新时间: 2024-11-04 01:08:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
21页 237K
描述
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

8432CY-51LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LQFP-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:8.57
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm湿度敏感等级:3
端子数量:32最高工作温度:70 °C
最低工作温度:最大输出时钟频率:700 MHz
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:50 MHz
座面最大高度:1.6 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

8432CY-51LF 数据手册

 浏览型号8432CY-51LF的Datasheet PDF文件第2页浏览型号8432CY-51LF的Datasheet PDF文件第3页浏览型号8432CY-51LF的Datasheet PDF文件第4页浏览型号8432CY-51LF的Datasheet PDF文件第5页浏览型号8432CY-51LF的Datasheet PDF文件第6页浏览型号8432CY-51LF的Datasheet PDF文件第7页 
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL  
LVPECL FREQUENCY SYNTHESIZER  
ICS8432-51  
GENERAL DESCRIPTION  
FEATURES  
The ICS8432-51 is a general purpose, dual output Crystal-to-  
3.3V Differential LVPECL High Frequency Synthesizer. The  
ICS8432-51 has a selectable REF_CLK or crystal input. The  
VCO operates at a frequency range of 250MHz to 700MHz. The  
VCO frequency is programmed in steps equal to the value of  
the input reference or crystal frequency. The VCO and output  
frequency can be programmed using the serial or parallel inter-  
face to the configuration logic. The low phase noise character-  
istics of the ICS8432-51 make it an ideal clock source for Giga-  
bit Ethernet, Fibre Channel 1 and 2, and Infiniband applica-  
tions.  
Dual differential 3.3V LVPECL outputs  
Selectable crystal oscillator interface or  
LVCMOS/LVTTL REF_CLK  
Output frequency range: 31.25MHz to 700MHz  
Crystal input frequency range: 12MHz to 25MHz  
VCO range: 250MHz to 700MHz  
Parallel or serial interface for programming counter and  
output dividers  
RMS period jitter: 3.5ps (maximum)  
Cycle-to-cycle jitter: 25ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Replaces the ICS8432-01  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
VCO_SEL  
XTAL_SEL  
M5  
M6  
M7  
M8  
N0  
N1  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL_OUT  
REF_CLK  
XTAL_SEL  
VCCA  
REF_CLK  
0
XTAL1  
1
OSC  
ICS8432-51  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
XTAL2  
VEE  
PLL  
9
10 11 12 13 14 15 16  
PHASE DETECTOR  
÷1  
MR  
0
1
VCO  
÷2  
÷4  
÷8  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
÷ M  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
Top View  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
M0:M8  
N0:N1  
Top View  
IDT/ ICS3.3V LVPECL FREQUENCY SYNTHESIZER  
1
ICS8432CY-51 REVISION F NOVEMBER 13, 2012  

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