ICS8430I-71
Integrated
Circuit
Systems, Inc.
700MH
Z, LOW
J
ITTER, CRYSTAL
I
NTERFACE
/
LVCMOS-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
12
12
27
27
50
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 27MHz, valid values of M are 75 ≤ M ≤ 208.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
27
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FMAX
Output Frequency
700
25
50
9
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
fOUT > 87.5MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
fOUT ≤ 87.5MHz
tjit(per)
tsk(o)
tR / tF
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
15
700
20% to 80%
200
5
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N ≠ div-by-1
48
45
52
55
N = div-by-1, fOUT ≤ 400MHz
N = div-by-1,
400MHz < fOUT ≤ 630MHz
%
odc
Output Duty Cycle
40
60
1
%
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430AYI-71
www.icst.com/products/hiperclocks.html
REV. B JANUARY 27, 2005
6