Datasheet > 8430AYI-71

8430AYI-71

更新时间： 2024-02-14 11:17:12

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	211K
描述
Clock Generator, PQFP32

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8430AYI-71 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	QFP, QFP32,.35SQ,32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.33
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e3
湿度敏感等级：	3	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Clock Generators	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

8430AYI-71 数据手册

ICS8430I-71

Integrated

Circuit

Systems, Inc.

700MH

Z, LOW

ITTER, CRYSTAL

NTERFACE

LVCMOS-TO-3.3V LVPECL FREQUENCY

SYNTHESIZER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Pulldown

Description

1, 2, 3,

28, 29, 30

31, 32

M5, M6, M7,

M0, M1, M2,

M3, M4

Input

M divider inputs. Data latched on LOW-to-HIGH transition of

nP_LOAD input. LVCMOS / LVTTL interface levels.

5, 6

N0, N1

Input

Power

Pullup

Pulldown

Pullup

Determines output divider value as defined in Table 3C

Function Table. LVCMOS / LVTTL interface levels.

8, 16

V_EE

Negative supply pins.

Test output which is ACTIVE in the serial mode of operation.

Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.

Core power supply pin.

TEST

Output

Power

Output

Power

Output

V_CC

FOUT1,

nFOUT1

V_CCO

FOUT0,

nFOUT0

11, 12

Differential output for the synthesizer. 3.3V LVPECL interface levels.

Output supply pin.

14, 15

Differential output for the synthesizer. 3.3V LVPECL interface levels.

Active High Master reset. When logic HIGH, the internal dividers are

reset causing the true outputs (FOUTx) to go low and the inverted

Input

Pulldown outputs (nFOUTx) to go high. When Logic LOW, the internal dividers

and the outputs are enabled. Assertion of MR does not affect loaded

M, N, and T values. LVCMOS / LVTTL interface levels.

Clocks in serial data present at S_DATA input into the shift register

on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.

Shift register serial input. Data sampled on the rising edge of

S_CLOCK. LVCMOS / LVTTL interface levels.

S_CLOCK

S_DATA

Input

Pulldown

Controls transition of data from shift register into the dividers.

LVCMOS / LVTTL interface levels.

Analog supply pin.

S_LOAD

V_CCA

Input

Pulldown

Power

Selects between the crystal oscillator or test clock as the

XTAL_SEL

Input

Pullup

PLL reference source. Selects XTAL inputs when HIGH.

Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.

TEST_CLK

Input

Pulldown Test clock input. LVCMOS interface levels.

24, 25

XTAL1, XTAL2

Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.

Parallel load input. Determines when data present at M8:M0 is

Pulldown loaded into the M divider, and when data present at N2:N0 sets the

N output divider value. LVCMOS / LVTTL interface levels.

nP_LOAD

Input

Determines whether synthesizer is in PLL or bypass mode.

LVCMOS / LVTTL interface levels.

VCO_SEL

Input

Pullup

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Capacitance

Input Pullup Resistor

KΩ

R_PULLUP

R_PULLDOWNInput Pulldown Resistor

8430AYI-71

www.icst.com/products/hiperclocks.html

REV. B JANUARY 27, 2005

1 234 5 6 7...16

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