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8344BYI PDF预览

8344BYI

更新时间: 2024-09-13 19:56:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 460K
描述
Low Skew Clock Driver, 8344 Series, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48

8344BYI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:8344
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G48
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.036 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):240
电源:2.5/3.3 VProp。Delay @ Nom-Sup:4.5 ns
传播延迟(tpd):4.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.275 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
Base Number Matches:1

8344BYI 数据手册

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LOW SKEW, 1-TO-24 DIFFERENTIAL-  
TO-LVCMOS/LVTTL FANOUT BUFFER  
ICS8344I  
GENERAL DESCRIPTION  
FEATURES  
The ICS8344I is a low voltage, low skew fanout  
Twenty-four LVCMOS/LVTTL outputs,  
7Ω typical output impedance  
ICS  
HiPerClockS™  
buffer and a member of the HiPerClockS™ fam-  
ily of High Performance Clock Solutions from IDT.  
Two selectable differential clock input pairs for redundant  
clock applications  
The ICS8344I has two selectable clock inputs.  
The CLK0, nCLK0 and CLK1, nCLK1 pairs can  
accept most standard differential input levels. The ICS8344I  
is designed to translate any differential signal levels to  
LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL  
outputs are designed to drive 50Ω series or parallel termi-  
nated transmission lines. The effective fanout can be in-  
creased to 48 by utilizing the ability of the outputs to drive  
two series terminated lines. Redundant clock applications  
can make use of the dual clock input. The dual clock inputs  
also facilitate board level testing. ICS8344I is character-  
ized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V  
output operating supply modes.  
CLKx, nCLKx pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency: 100MHz  
Translates any single-ended input signal to LVCMOS/LVTTL  
with resistor bias on nCLK input  
Multiple output enable pins for disabling unused outputs  
in reduced fanout applications  
Output skew: 275ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Bank skew: 150ps (maximum)  
Guaranteed output and part-to-part skew characteristics make  
the ICS8344I ideal for those clock distribution applications de-  
manding well defined performance and repeatability.  
Supply modes:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
2.5V/2.5V  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
48 47 46 45 44 43 42 41 40 39 38 37  
Q16  
Q17  
VDDO  
GND  
Q18  
Q19  
Q20  
Q21  
VDDO  
GND  
Q22  
Q23  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q7  
CLK0  
nCLK0  
2
Q6  
0
3
VDDO  
GND  
Q5  
CLK1  
1
4
ICS8344I  
nCLK1  
Q0:Q7  
OE1  
5
48-Lead LQFP  
7mm x 7mm x 1.4mm  
package body  
Y Package  
6
Q4  
7
Q3  
8
Q2  
Q8:Q15  
9
VDDO  
GND  
Q1  
Top View  
10  
11  
12  
OE2  
Q16:Q23  
Q0  
13 14 15 16 17 18 19 20 21 22 23 24  
OE3  
IDT/ ICSLVCMOS/LVTTL FANOUT BUFFER  
1
ICS8344BYI REV. B February 20, 2009  

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