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8344BYLFT PDF预览

8344BYLFT

更新时间: 2024-10-31 08:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 136K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

8344BYLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
其他特性:CAN ALSO OPERATE WITH A 3.3V SUPPLY系列:8344
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.036 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:4.5 ns
传播延迟(tpd):4.3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.275 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

8344BYLFT 数据手册

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ICS8344  
LOW SKEW, 1-TO-24  
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8344 is a low voltage, low skew, 1-to-24 Differential-  
to-LVCMOS Fanout Buffer.The ICS8344 is designed to trans-  
late any differential signal levels to LVCMOS levels. The low  
impedance LVCMOS outputs are designed to drive 50Ω se-  
ries or parallel terminated transmission lines. The effective  
fanout can be increased to 48 by utilizing the ability of the  
outputs to drive two series terminated lines. Redundant clock  
applications can make use of the dual clock input. The dual  
clock inputs also facilitate board level testing. ICS8344 is  
characterized at full 3.3V, full 2.5V and mixed 3.3V input and  
2.5V output operating supply modes.  
Twenty-four LVCMOS outputs, 7Ω typical output impedance  
Selectable differential clock input pairs for redundant  
clock applications  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency: 167MHz  
Translates any differential input signal (LVPECL, LVHSTL,  
LVDS) to LVCMOS without external bias networks  
Translates any single-ended input signal to LVCMOS  
with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS8344 ideal for those clock distribution applica-  
tions demanding well defined performance and repeatability.  
Multiple output enable pins for disabling unused outputs  
in reduced fanout applications  
Output skew: 275ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Bank skew: 150ps (maximum)  
Propagation Delay: 4.3ns (maximum)  
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes  
0°C to 70°C ambient operating temperature  
Available in standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
48 47 46 45 44 43 42 41 40 39 38 37  
Q16  
Q17  
VDDO  
GND  
Q18  
Q19  
Q20  
Q21  
VDDO  
GND  
Q22  
Q23  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q7  
CLK0  
nCLK0  
2
Q6  
0
3
VDDO  
GND  
Q5  
CLK1  
1
nCLK1  
4
5
Q0:Q7  
6
Q4  
ICS8344  
7
Q3  
OE1  
8
Q2  
O8:Q15  
9
VDDO  
GND  
Q1  
10  
11  
12  
OE2  
O16:Q23  
Q0  
13 14 15 16 17 18 19 20 21 22 23 24  
OE3  
48-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8344BY  
1
REV.A JANUARY 5, 2011  

8344BYLFT 替代型号

型号 品牌 替代类型 描述 数据表
8344AYI-01LF IDT

完全替代

Low Skew, 1-to-24 Differential-to-LVCMOS/LVTTL Fanout Buffer
8344AY-01LF IDT

完全替代

LOW SKEW, 1-TO-24 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER

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