5秒后页面跳转
74VHCT595D PDF预览

74VHCT595D

更新时间: 2024-09-17 11:09:47
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
20页 297K
描述
8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction

74VHCT595D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
计数方向:RIGHT系列:AHCT/VHCT/VT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:SERIAL IN SERIAL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):12 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:90 MHzBase Number Matches:1

74VHCT595D 数据手册

 浏览型号74VHCT595D的Datasheet PDF文件第2页浏览型号74VHCT595D的Datasheet PDF文件第3页浏览型号74VHCT595D的Datasheet PDF文件第4页浏览型号74VHCT595D的Datasheet PDF文件第5页浏览型号74VHCT595D的Datasheet PDF文件第6页浏览型号74VHCT595D的Datasheet PDF文件第7页 
74VHC595; 74VHCT595  
8-bit serial-in/serial-out or parallel-out shift register with  
output latches  
Rev. 3 — 25 June 2020  
Product data sheet  
1. General description  
The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin compatible with  
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.  
The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and 3-state  
outputs. The shift registers have separate clocks.  
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data  
in each register is transferred to the storage register on a positive-going transition of the storage  
register clock input (STCP). If both clocks are connected together, the shift register will always be  
one clock pulse ahead of the storage register.  
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is  
also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage  
register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output  
whenever the output enable input (OE) is LOW.  
2. Features and benefits  
Balanced propagation delays  
All inputs have Schmitt-trigger action  
Inputs accept voltages higher than VCC  
Input levels:  
For 74VHC595: CMOS level  
For 74VHCT595: TTL level  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Applications  
Serial-to-parallel data conversion  
Remote control holding register  
 
 
 

与74VHCT595D相关器件

型号 品牌 获取价格 描述 数据表
74VHCT595D,118 NXP

获取价格

74VHC595; 74VHCT595 - 8-bit serial-in_serial-out or parallel-out shift register SOP 16-Pin
74VHCT595D-Q100 NXP

获取价格

IC AHCT/VHCT/VT SERIES, 8-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO
74VHCT595D-Q100 NEXPERIA

获取价格

8-bit serial-in/serial-out or parallel-out shift register with output latches
74VHCT595D-Q100J NXP

获取价格

74VHC(T)595-Q100 - 8-bit serial-in/serial-out or parallel-out shift register with output l
74VHCT595PW NXP

获取价格

8-bit serial-in/serial-out or parallel-out shift register with output latches
74VHCT595PW NEXPERIA

获取价格

8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction
74VHCT595PW,118 NXP

获取价格

74VHC595; 74VHCT595 - 8-bit serial-in_serial-out or parallel-out shift register TSSOP 16-P
74VHCT595PW-Q100 NEXPERIA

获取价格

8-bit serial-in/serial-out or parallel-out shift register with output latches
74VHCT595PW-Q100J NXP

获取价格

74VHC(T)595-Q100 - 8-bit serial-in/serial-out or parallel-out shift register with output l
74VHCT595-Q100 NEXPERIA

获取价格

8-bit serial-in/serial-out or parallel-out shift register with output latches