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74VHCT74ASJX PDF预览

74VHCT74ASJX

更新时间: 2024-11-24 23:24:39
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 82K
描述
Dual D-Type Flip-Flop

74VHCT74ASJX 数据手册

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July 1997  
Revised April 1999  
74VHCT74A  
Dual D-Type Flip-Flop with Preset and Clear  
output voltages. This device can be used to interface 3V to  
5V systems and two supply systems such as battery  
backup.  
General Description  
The VHCT74A is an advanced high speed CMOS Dual D-  
Type Flip-Flop fabricated with silicon gate CMOS technol-  
ogy. It achieves the high speed operation similar to equiva-  
lent Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation. The signal level applied to the D INPUT  
is transferred to the Q OUTPUT during the positive going  
transition of the CK pulse. CLR and PR are independent of  
the CK and are accomplished by setting the appropriate  
input LOW.  
Features  
High speed: fMAX = 160 MHz (typ) at TA = 25°C  
High noise immunity: VIH = 2.0V, VIL = 0.8V  
Power down protection is provided on all inputs and  
outputs  
Low power dissipation:  
Protection circuits ensure that 0V to 7V can be applied to  
the input pins without regard to the supply voltage and to  
the output pins with VCC = 0V. These circuits prevent  
ICC = 2 µA (max) at TA = 25°C  
Pin and function compatible with 74HCT74  
device destruction due to mismatched supply and input/  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHCT74AM  
74VHCT74ASJ  
74VHCT74AMTC  
74VHCT74AN  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Truth Table  
Pin Names  
D1, D2  
Description  
Data Inputs  
Inputs  
CLR PR  
Outputs  
Function  
D
CK  
X
Q
L
Q
H
L
L
H
L
H
L
X
X
X
L
Clear  
CK1, CK2  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Preset Inputs  
Outputs  
X
H
H
L
Preset  
CLR1, CLR2  
PR1, PR2  
L
X
H
H
L
H
H
H
H
H
H
Q1, Q1, Q2, Q2  
H
X
H
Qn  
Qn No  
Change  
© 1999 Fairchild Semiconductor Corporation  
DS500026.prf  
www.fairchildsemi.com  

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