Datasheet > 74VHCT9125AFT

74VHCT9125AFT

更新时间： 2024-11-21 14:56:15

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
9页	179K
描述
5-bit Buffer, TSSOP14B

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74VHCT9125AFT 数据手册

74VHCT9125AFT,74VHCT9126AFT

CMOS Digital Integrated Circuits Silicon Monolithic

74VHCT9125AFT,74VHCT9126AFT

1. Functional Description

•

5-Bit Universal Schmitt Buffer with 3-State Outputs

2. General

The 74VHCT9125AFT/74VHCT9126AFT are an ultra-high-speed 5-bit Schmitt buffer fabricated using silicon-

gate CMOS technology. The 74VHCT9125AFT/74VHCT9126AFT combines low power consumption of CMOS

with Schottky TTL speeds.

The input voltage are compatible with TTL output voltage.

This device may be used as a level converter for interfacing 3.3 V to 5 V system.

Y1 to Y4 outputs can be put in the high-impedance state by placing a logic HIGH on the Enable (G) input. The

CONT input determines the logical inversion of data. A logic LOW on the CONT input configures the

74VHCT9125AFT/74VHCT9126AFT as an inverter; a logic HIGH on the CONT input configures the

74VHCT9125AFT/74VHCT9126AFT as a buffer.

74VHCT9125AFT Y5 output is an inverting type, and the 74VHCT9126AFT Y5 output is a non-inverting type.

All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the

74VHCT9125AFT/74VHCT9126AFT are capable of squaring up transitions of slowly changing input signals and

provides an improved noise immunity.

Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins

without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and

input/output voltages such as battery back up, etc.

Note: Output in off-state

3. Features

(1) AEC-Q100 (Rev. H) (Note 1)

(2) Wide operating temperature range: Topr = -40 to 125 

(3) High speed: Propagation delay time = 6.6 ns (typ.) at VCC = 5.0 V

(4) Quiescent supply current: ICC = 2.0 µA (max) at Ta = 25 

(5) Compatible with TTL input: VIL = 0.5 V(max)

VIH = 2.1 V(min)

(6) Power down protection is provided on all inputs and outputs.

(7) Balanced propagation delays: tPLH ≈ tPHL

(8) Input terminals are at the opposite side of Output terminals

Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales

representative.

Start of commercial production

2015-02

2016-08-05

Rev.2.0

12 3 4 5 6 7...9

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