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74VHC175_07 PDF预览

74VHC175_07

更新时间: 2024-11-16 04:48:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
9页 253K
描述
Quad D-Type Flip-Flop

74VHC175_07 数据手册

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May 2007  
74VHC175  
tm  
Quad D-Type Flip-Flop  
Features  
General Description  
High Speed: f  
= 210MHz (Typ.) at V = 5V  
The VHC175 is an advanced high-speed CMOS device  
fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
MAX  
CC  
Low power dissipation: I = 4µA (Max.) at T = 25°C  
High noise immunity: V  
CC  
A
= V  
= 28% V (Min.)  
NIH  
NIL  
CC  
Power down protection is provided on all inputs  
Low noise: V = 0.8V (Max.)  
OLP  
The VHC175 is a high-speed quad D-type flip-flop. The  
device is useful for general flip-flop requirements where  
clock and clear inputs are common. The information on  
the D inputs is stored during the LOW-to-HIGH clock  
transition. Both true and complemented outputs of each  
flip-flop are provided. A Master Reset input resets all flip-  
flops, independent of the Clock or D inputs, when LOW.  
Pin and function compatible with 74HC175  
An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply  
voltage. This device can be used to interface 5V to 3V  
systems and two supply systems such as battery  
backup. This circuit prevents device destruction due to  
mismatched supply and input voltages.  
Ordering Information  
Package  
Order Number  
74VHC175M  
Number  
Package Description  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74VHC175SJ  
74VHC175MTC  
M16D  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the  
ordering number.  
Connection Diagram  
Pin Description  
Pin Names  
Description  
D –D  
Data Inputs  
0
3
CP  
Clock Pulse Input  
Master Reset Input  
True Outputs  
MR  
Q –Q  
0
3
Q –Q  
Complement Outputs  
0
3
©1993 Fairchild Semiconductor Corporation  
74VHC175 Rev. 1.2  
www.fairchildsemi.com  

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