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74VHC20M PDF预览

74VHC20M

更新时间: 2024-11-04 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
7页 54K
描述
DUAL 4-INPUT NAND GATE

74VHC20M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.38
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.008 A功能数量:2
输入次数:4端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):11.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

74VHC20M 数据手册

 浏览型号74VHC20M的Datasheet PDF文件第2页浏览型号74VHC20M的Datasheet PDF文件第3页浏览型号74VHC20M的Datasheet PDF文件第4页浏览型号74VHC20M的Datasheet PDF文件第5页浏览型号74VHC20M的Datasheet PDF文件第6页浏览型号74VHC20M的Datasheet PDF文件第7页 
74VHC20  
DUAL 4-INPUT NAND GATE  
PRELIMINARY DATA  
HIGH SPEED:tPD =3.3ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =2 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
VNIH = VNIL =28% VCC (MIN.)  
M
T
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC20M  
74VHC20T  
immunity and stable output.  
OPERATING VOLTAGERANGE:  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES20  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC20 is an advanced high-speed CMOS  
DUAL 4-INPUT NAND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
June 1999  

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