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74VHC175MTCX PDF预览

74VHC175MTCX

更新时间: 2024-11-19 23:24:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 74K
描述
Quad D-Type Flip-Flop

74VHC175MTCX 数据手册

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August 1993  
Revised April 1999  
74VHC175  
Quad D-Type Flip-Flop  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC175 is an advanced high-speed CMOS device  
fabricated with silicon gate CMOS technology. It achieves  
the high-speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining the CMOS low power dissi-  
pation.  
Features  
High Speed: fMAX = 210 MHz (typ) at VCC = 5V  
Low power dissipation: ICC = 4 µA (max) at TA = 25°C  
High noise immunity: VNIH = VNIL = 28% VCC (min)  
The VHC175 is a high-speed quad D-type flip-flop. The  
device is useful for general flip-flop requirements where  
clock and clear inputs are common. The information on the  
D inputs is stored during the LOW-to-HIGH clock transition.  
Both true and complemented outputs of each flip-flop are  
provided. A Master Reset input resets all flip-flops, inde-  
pendent of the Clock or D inputs, when LOW.  
Power down protection is provided on all inputs  
Low noise: VOLP = 0.8V (max)  
Pin and function compatible with 74HC175  
An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC175M  
74VHC175SJ  
74VHC175MTC  
74VHC175N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
D0–D3  
CP  
Description  
Data Inputs  
Clock Pulse Input  
Master Reset Input  
True Outputs  
MR  
Q0–Q3  
Q0–Q 3  
Complement Outputs  
Logic Symbols  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS011637.prf  
www.fairchildsemi.com  

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