Datasheet > 74VCXR162601_04

74VCXR162601_04

更新时间： 2024-09-15 04:48:03

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
9页	140K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in the Outputs

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74VCXR162601_04 数据手册

August 1998

Revised October 2004

74VCXR162601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and

Outputs and 26Ω Series Resistors in the Outputs

General Description

The VCXR162601, 18-bit universal bus transceiver, com-

bines D-type latches and D-type flip-flops to allow data flow

in transparent, latched, and clocked modes.

Features

■ 1.4V to 3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ 26Ω series resistors on both the A and B Port outputs.

■ t_PD(A to B, B to A)

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the high-impedance state.

3.8 ns max for 3.0V to 3.6V V_CC

■ Power-down HIGH impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Static Drive (I_OH/I_OL

)

±12 mA @ 3.0V V_CC

■ Uses patented noise/EMI reduction circuitry

■ Latchup performance exceeds 300 mA

■ ESD performance:

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

Human body model > 2000V

The 74VCXR162601 is designed for low voltage (1.4V to

3.6V) V_CCapplications with I/O compatibility up to 3.6V.

Machine model >200V

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

The VCXR162601 is also designed with 26Ω series resis-

tors on both the A and B Port outputs. This design reduces

line noise in applications such as memory address drivers,

clock drivers, and bus transceivers/transmitters.

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Package

Order Number

Package Description

Number

74VCXR162601MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS500171

www.fairchildsemi.com

12 3 4 5 6 7...9

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与74VCXR162601_04相关器件

型号	品牌	获取价格	描述	数据表
74VCXR162601MTD	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Transceivers
74VCXR162601MTDX	FAIRCHILD	获取价格	18-Bit Bus Transceiver
74VCXR162601MTX	FAIRCHILD	获取价格	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56,
74VHC00	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NAND GATE
74VHC00	FAIRCHILD	获取价格	Quad 2-Input NAND Gate
74VHC00_04	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NAND GATE
74VHC00_08	FAIRCHILD	获取价格	Quad 2-Input NAND Gate
74VHC00FT	TOSHIBA	获取价格	Quad 2-Input/NAND, TSSOP14B
74VHC00M	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NAND GATE
74VHC00M	FAIRCHILD	获取价格	Quad 2-Input NAND Gate

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