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74VCXR162601MTDX PDF预览

74VCXR162601MTDX

更新时间： 2024-11-04 23:24:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
7页 63K
描述
18-Bit Bus Transceiver

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74VCXR162601MTDX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：compliant
风险等级：5.57其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
负载电容（CL）：30 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.012 A位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：3.8 ns
传播延迟（tpd）：18.4 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.4 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74VCXR162601MTDX 数据手册

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August 1998  
Revised April 1999  
74VCXR162601  
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V  
Tolerant Inputs and Outputs and 26Ω Series Resistors in  
the Outputs  
General Description  
The VCXR162601, 18-bit universal bus transceiver, com-  
bines D-type latches and D-type flip-flops to allow data flow  
in transparent, latched, and clocked modes.  
Features  
■ 1.65–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ 26Ω series resistors on both the A and B Port outputs.  
■ tPD (A to B, B to A)  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. The clock can be con-  
trolled by the clock-enable (CLKENAB and CLKENBA)  
inputs. For A-to-B data flow, the device operates in the  
transparent mode when LEAB is HIGH. When LEAB is  
LOW, the A data is latched if CLKAB is held at a HIGH-to-  
LOW logic level. If LEAB is LOW, the A bus data is stored  
in the latch/flip-flop on the LOW-to-HIGH transition of  
CLKAB. Output-enable OEAB is active-LOW. When OEAB  
is HIGH, the outputs are in the high-impedance state.  
3.8 ns max for 3.0V to 3.6V VCC  
4.6 ns max for 2.3V to 2.7V VCC  
9.2 ns max for 1.65V to 1.95V VCC  
■ Power-down HIGH impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
■ Static Drive (IOH/IOL  
)
±12 mA @ 3.0V VCC  
±8 mA @ 2.3V VCC  
±3 mA @ 1.65V VCC  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, CLKBA and CLKENBA.  
The 74VCXR162601 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup performance exceeds 300 mA  
■ ESD performance:  
The VCXR162601 is also designed with 26Ω series resis-  
tors on both the A and B Port outputs. This design reduces  
line noise in applications such as memory address drivers,  
clock drivers, and bus transceivers/transmitters.  
Human body model > 2000V  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCXR162601MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 1999 Fairchild Semiconductor Corporation  
DS500171.prf  
www.fairchildsemi.com  
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