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74VCX16500MTD PDF预览

74VCX16500MTD

更新时间： 2024-11-08 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 64K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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74VCX16500MTD 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.61
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：2
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：29 ns
传播延迟（tpd）：19.6 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.4 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：NEGATIVE EDGE宽度：6.1 mm

74VCX16500MTD 数据手册

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March 1998  
Revised April 1999  
74VCX16500  
Low Voltage 18-Bit Universal Bus Transceivers with  
3.6V Tolerant Inputs and Outputs  
General Description  
The VCX16500 is an 18-bit universal bus transceiver which  
combines D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, and clocked modes.  
Features  
■ 1.65V–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ tPD (A to B, B to A)  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the HIGH-to-LOW  
transition of CLKAB. When OEAB is HIGH, the outputs are  
active. When OEAB is LOW, the outputs are in a high-  
impedance state.  
2.9 ns max for 3.0V to 3.6V VCC  
3.5 ns max for 2.3V to 2.7V VCC  
7.0 ns max for 1.65V to 1.95V VCC  
■ Power-down high impedance inputs and outputs  
■ Supports live insertion/withdrawal (Note 1)  
■ Static Drive (IOH/IOL  
)
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup performance exceeds 300 mA  
■ ESD performance:  
The VCX16500 is designed for low voltage (1.65V to 3.6V)  
VCC applications with I/O capability up to 3.6V.  
Human body model > 2000V  
The 74VCX16500 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OEBA should be tied to V  
through a pull-up resistor and OEAB  
CC  
should be tied to GND through a pull-down resistors; the minimum value of  
the resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16500MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 1999 Fairchild Semiconductor Corporation  
DS500089.prf  
www.fairchildsemi.com  
12345678

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