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74V1T05CTR PDF预览

74V1T05CTR

更新时间: 2024-11-04 21:21:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 62K
描述
74V SERIES, 1-INPUT INVERT GATE, PDSO5, SOT-323, 5 PIN

74V1T05CTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SC-70包装说明:SOT-323, 5 PIN
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
系列:74VJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.25 mm
Base Number Matches:1

74V1T05CTR 数据手册

 浏览型号74V1T05CTR的Datasheet PDF文件第2页浏览型号74V1T05CTR的Datasheet PDF文件第3页浏览型号74V1T05CTR的Datasheet PDF文件第4页浏览型号74V1T05CTR的Datasheet PDF文件第5页浏览型号74V1T05CTR的Datasheet PDF文件第6页浏览型号74V1T05CTR的Datasheet PDF文件第7页 
74V1T05  
SINGLE INVERTER (OPEN DRAIN)  
HIGH SPEED: t =5.4ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUT  
SOT23-5L  
SOT323-5L  
T & R  
OPERATING VOLTAGE RANGE:  
V
(OPR) = 4.5V to 5.5V  
CC  
IMPROVED LATCH-UP IMMUNITY  
ORDER CODES  
PACKAGE  
DESCRIPTION  
SOT23-5L  
74V1T05STR  
74V1T05CTR  
The 74V1T05 is an advanced high-speed CMOS  
SINGLE INVERTER (OPEN DRAIN) fabricated  
with sub-micron silicon gate and double-layer  
SOT323-5L  
2
metal wiring C MOS technology.  
Power down protection is provided on input and 0  
to 7V can be accepted on input with no regard to  
the supply voltage. This device can be used to  
interface 5V to 3V.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/9  

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