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74V1T125 PDF预览

74V1T125

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 58K
描述
SINGLE BUS BUFFER 3-STATE

74V1T125 数据手册

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74V1T125  
SINGLE BUS BUFFER (3-STATE)  
HIGH SPEED:tPD =3.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =1 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUT  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
S
C
(SOT23-5L)  
(SC-70)  
ORDER CODE:  
74V1T125S  
3-STATE control input G has to be set high to  
place the output into the high impedance state.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
DESCRIPTION  
The 74V1T125 is an advanced high-speed  
CMOS SINGLE BUS BUFFER fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
October 1999  

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