Datasheet > 74LVTH273SJX

74LVTH273SJX

更新时间： 2024-11-08 23:24:31

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管信息通信管理
页数	文件大小	规格书
7页	81K
描述
Octal D-Type Flip-Flop

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74LVTH273SJX 数据手册

July 1999

Revised November 2000

74LVTH273

Low Voltage Octal D-Type Flip-Flop with Clear

General Description

Features

The LVTH273 is a high-speed, low-power positive-edge-

triggered octal D-type flip-flop featuring separate D-type

inputs for each flip-flop. A buffered Clock (CP) and Clear

(CLR) are common to all flip-flops.

■ Input and output interface capability to systems at

5V V_CC

■ Bushold on the data inputs eliminate the need for

external pull-up resistors to hold unused inputs

The state of each D-type input, one setup time before the

positive clock transition, is transferred to the corresponding

flip-flop’s output.

■ Outputs source/sink −32 mA/+64 mA

■ Functionally compatible with the 74 series 273

■ Latch-up performance exceeds 500 mA

■ ESD performance:

The LVTH273 data inputs include bushold, eliminating the

need for external pull-up resistors to hold unused inputs.

Human-body model > 2000V

These octal flip-flops are designed for low-voltage (3.3V)

V_CCapplications, but with the capability to provide a TTL

Machine model > 200V

interface to a 5V environment. The LVTH273 is fabricated

with an advanced BiCMOS technology to achieve high

speed operation similar to 5V ABT while maintaining low

power dissipation.

Charged-device model > 1000V

Ordering Code:

Order Number Package Number

Package Description

74LVTH273WM

74LVTH273SJ

74LVTH273MTC

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

DS500100

www.fairchildsemi.com

12 3 4 5 6 7

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