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74LVTH273WMX_NL PDF预览

74LVTH273WMX_NL

更新时间: 2024-11-09 12:59:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 98K
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74LVTH273WMX_NL 数据手册

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July 1999  
Revised March 2005  
74LVTH273  
Low Voltage Octal D-Type Flip-Flop with Clear  
General Description  
Features  
The LVTH273 is a high-speed, low-power positive-edge-  
triggered octal D-type flip-flop featuring separate D-type  
inputs for each flip-flop. A buffered Clock (CP) and Clear  
(CLR) are common to all flip-flops.  
Input and output interface capability to systems at  
5V VCC  
Bushold on the data inputs eliminate the need for  
external pull-up resistors to hold unused inputs  
The state of each D-type input, one setup time before the  
positive clock transition, is transferred to the corresponding  
flip-flop’s output.  
Outputs source/sink 32 mA/ 64 mA  
Functionally compatible with the 74 series 273  
Latch-up performance exceeds 500 mA  
ESD performance:  
The LVTH273 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
Human-body model 2000V  
These octal flip-flops are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
Machine model 200V  
interface to a 5V environment. The LVTH273 is fabricated  
with an advanced BiCMOS technology to achieve high  
speed operation similar to 5V ABT while maintaining low  
power dissipation.  
Charged-device model 1000V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVTH273WM  
74LVTH273SJ  
74LVTH273MTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MTC20  
MTC20  
74LVTH273MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbols  
IEEE/IEC  
© 2005 Fairchild Semiconductor Corporation  
DS500100  
www.fairchildsemi.com  

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