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74LVTH32373GX PDF预览

74LVTH32373GX

更新时间： 2024-09-15 22:36:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路信息通信管理
页数 文件大小 规格书
6页 163K
描述
Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

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74LVTH32373GX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA96,6X16,32
针数：96Reach Compliance Code：compliant
风险等级：5.56Is Samacsys：N
系列：LVTJESD-30 代码：R-PBGA-B96
JESD-609代码：e0长度：13.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A湿度敏感等级：3
位数：8功能数量：4
端口数量：2端子数量：96
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA96,6X16,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
传播延迟（tpd）：4.8 ns认证状态：Not Qualified
座面最大高度：1.4 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.5 mm
Base Number Matches：1

74LVTH32373GX 数据手册

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Preliminary  
August 2001  
Revised August 2001  
74LVT32373 • 74LVTH32373  
Low Voltage 32-Bit Transparent Latch  
with 3-STATE Outputs (Preliminary)  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT32373 and LVTH32373 contain thirty-two non-  
inverting latches with 3-STATE outputs and are intended  
for bus oriented applications. The device is byte controlled.  
The flip-flops appear transparent to the data when the  
Latch Enable (LE) is HIGH. When LE is LOW, the data that  
meets the setup time is latched. Data appears on the bus  
when the Output Enable (OE) is LOW. When OE is HIGH,  
the outputs are in a high impedance state.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH32373),  
also available without bushold feature (74LVT32373)  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH32373 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Outputs source/sink −32 mA/+64 mA  
■ ESD performance:  
These latches are designed for low-voltage (3.3V) VCC  
Human-body model > 2000V  
Machine model > 200V  
applications, but with the capability to provide a TTL inter-  
face to a 5V environment. The LVT32373 and LVTH32373  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining a low power dissipation.  
Charged-device model > 1000V  
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)  
(Preliminary)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT32373GX  
(Note 1)  
BGA96A  
(Preliminary)  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
74LVTH32373GX  
(Note 1)  
BGA96A  
(Preliminary)  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
Note 1: BGA package available in Tape and Reel only.  
Logic Symbol  
© 2001 Fairchild Semiconductor Corporation  
DS500548  
www.fairchildsemi.com  
123456

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