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74LVT273BQ PDF预览

74LVT273BQ

更新时间: 2024-09-16 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
17页 107K
描述
3.3 V octal D-type flip-flop

74LVT273BQ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT764-1, DHVQFN-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
系列:LVTJESD-30 代码:R-PQCC-N20
长度:4.5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC20,.1X.18,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:5.5 ns认证状态:Not Qualified
座面最大高度:1 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:AUTOMOTIVE
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
Base Number Matches:1

74LVT273BQ 数据手册

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74LVT273  
3.3 V octal D-type flip-flop  
Rev. 03 — 10 September 2008  
Product data sheet  
1. General description  
The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at  
3.3 V.  
This device has eight edge-triggered D-type flip-flops with individual D inputs and Q  
outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset  
(clear) all flip-flops simultaneously.  
The register is fully edge-triggered. The state of each D input, one setup time before the  
LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.  
All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage  
level on the MR input. The device is useful for applications where only the true output is  
required and the CP and MR are common elements.  
2. Features  
I Eight edge-triggered D-type flip-flops  
I Buffered common clock and asynchronous master reset  
I Input and output interface capability to systems at 5 V supply  
I TTL input and output switching levels  
I Input and output interface capability to systems at 5 V supply  
I Output capability: +64 mA/32 mA  
I Latch-up protection  
N JESD78 Class II exceeds 500 mA  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs  
I Live insertion/extraction permitted  
I Power-up reset  
I No bus current loading when output is tied to 5 V bus  

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