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74LVT16245MEA_NL PDF预览

74LVT16245MEA_NL

更新时间： 2024-11-18 21:20:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
8页 91K
描述
Bus Transceiver, LVT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48

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74LVT16245MEA_NL 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknown风险等级：5.57
其他特性：WITH DIRECTION CONTROL系列：LVT
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：15.875 mm逻辑集成电路类型：BUS TRANSCEIVER
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：3.9 ns认证状态：Not Qualified
座面最大高度：2.74 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.495 mm
Base Number Matches：1

74LVT16245MEA_NL 数据手册

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January 1999  
Revised June 2005  
74LVT16245 • 74LVTH16245  
Low Voltage 16-Bit Transceiver with 3-STATE Outputs  
General Description  
Features  
The LVT16245 and LVTH16245 contain sixteen non-invert-  
ing bidirectional buffers with 3-STATE outputs and is  
intended for bus oriented applications. The device is byte  
controlled. Each byte has separate control inputs which  
can be shorted together for full 16-bit operation. The T/R  
inputs determine the direction of data flow through the  
device. The OE inputs disable both the A and B ports by  
placing them in a high impedance state.  
■ Input and output interface capability to systems at  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16245),  
also available without bushold feature (74LVT16245).  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH16245 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 16245  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These non-inverting transceivers are designed for low-volt-  
age (3.3V) VCC applications, but with the capability to pro-  
vide a TTL interface to a 5V environment. The LVT16245  
and LVTH16245 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining low power dissipation.  
Human-body model 2000V  
Machine model 200V  
Charged-device 1000V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT16245GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[Tape and Reel]  
74LVT16245MEA  
(Note 2)  
MS48A  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16245MTD  
(Note 2)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16245GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[Tape and Reel]  
74LVTH16245MEA  
(Note 2)  
MS48A  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVTH16245MTD  
(Note 2)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 1: BGA package available in Tape and Reel only.  
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS500152  
www.fairchildsemi.com  
12345678

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74LVT16245MEA_NL 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH16245ADLR TI

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