74LVT16373

更新时间： 2024-11-17 22:34:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		锁存器
页数	文件大小	规格书
8页	100K
描述
Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs

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中文翻译

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数据手册

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74LVT16373 数据手册

January 1999

Revised June 2005

74LVT16373 • 74LVTH16373

Low Voltage 16-Bit Transparent Latch

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16373 and LVTH16373 contain sixteen non-invert-

ing latches with 3-STATE outputs and is intended for bus

oriented applications. The device is byte controlled. The

flip-flops appear transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16373),

also available without bushold feature (74LVT16373)

■ Live insertion/extraction permitted

■ Power Up/Power Down high impedance provides

glitch-free bus loading

The LVTH16373 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Outputs source/sink 32 mA/ 64 mA

■ Functionally compatible with the 74 series 16373

■ Latch-up performance exceeds 500 mA

■ ESD performance:

These latches are designed for low-voltage (3.3V) V_CC

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT16373 and LVTH16373

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Human-body model 2000V

Machine model 200V

Charged-device model 1000V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Ordering Code:

Order Number

Package Number

Package Description

74LVT16373GX

(Note 1)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LVT16373MEA

(Note 2)

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16373MTD

(Note 2)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16373GX

(Note 1)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LVTH16373MEA

(Note 2)

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16373MTD

(Note 2)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 1: BGA package available in Tape and Reel only.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS012021

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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与74LVT16373相关器件

型号	品牌	获取价格	描述	数据表
74LVT16373A	NXP	获取价格	3.3V LVT 16-bit transparent D-type latch 3-State
74LVT16373ADGG	NXP	获取价格	3.3V LVT 16-bit transparent D-type latch 3-State
74LVT16373ADGG	NEXPERIA	获取价格	3.3 V 16-bit transparent D-type latch; 3-stateProduction
74LVT16373ADGG,512	NXP	获取价格	74LVT16373A - 3.3V LVT 16-bit transparent D-type latch (3-State) TSSOP 48-Pin
74LVT16373ADGG,518	NXP	获取价格	74LVT16373A - 3.3V LVT 16-bit transparent D-type latch (3-State) TSSOP 48-Pin
74LVT16373ADGG-T	NXP	获取价格	LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, SOT-362-1, TSSOP2-48
74LVT16373ADG-T	NXP	获取价格	IC LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVT16373ADL	NXP	获取价格	3.3V LVT 16-bit transparent D-type latch 3-State
74LVT16373ADL,112	NXP	获取价格	74LVT16373A - 3.3 V 16-bit transparent D-type latch; 3-state@en-us SSOP 48-Pin
74LVT16373ADL,118	NXP	获取价格	74LVT16373A - 3.3V LVT 16-bit transparent D-type latch (3-State) SSOP 48-Pin

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