74LVT16374

更新时间： 2024-11-17 22:56:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
8页	101K
描述
Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs

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中文翻译

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数据手册

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74LVT16374 数据手册

January 1999

Revised June 2005

74LVT16374 • 74LVTH16374

Low Voltage 16-Bit D-Type Flip-Flop

with 3-STATE Outputs

General Description

Features

■ Input and output interface capability to systems at

The LVT16374 and LVTH16374 contain sixteen non-invert-

ing D-type flip-flops with 3-STATE outputs and is intended

for bus oriented applications. The device is byte controlled.

A buffered clock (CP) and Output Enable (OE) are com-

mon to each byte and can be shorted together for full 16-bit

operation.

5V V_CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16374),

also available without bushold feature (74LVT16374)

■ Live insertion/extraction permitted

The LVTH16374 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Power Up/Power Down high impedance provides

glitch-free bus loading

■ Outputs source/sink 32 mA/ 64 mA

■ Functionally compatible with the 74 series 16374

■ Latch-up performance exceeds 500 mA

■ ESD performance:

These flip-flops are designed for low-voltage (3.3V) V_CC

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT16374 and LVTH16374

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Human-body model 2000V

Machine model 200V

Charged-device model 1000V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Order Number

Package Number

Package Description

74LVT16374G

BGA54A

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

(Note 1)(Note 2)

(Preliminary)

74LVT16374MEA

(Note 2)

MS48A

MTD48

BGA54A

MS48A

MTD48

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVT16374MTD

(Note 2)

74LVTH16374G

(Note 1)(Note 2)

74LVTH16374MEA

(Note 2)

74LVTH16374MTD

(Note 2)

Note 1: Ordering code “G” indicates Trays.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS012022

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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与74LVT16374相关器件

型号	品牌	获取价格	描述	数据表
74LVT16374A	NXP	获取价格	3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State
74LVT16374ADGG	NXP	获取价格	3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State
74LVT16374ADGG	NEXPERIA	获取价格	3.3 V 16-bit edge-triggered D-type flip-flop; 3-stateProduction
74LVT16374ADGG,112	NXP	获取价格	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48
74LVT16374ADGG,118	NXP	获取价格	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48
74LVT16374ADGG,512	NXP	获取价格	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48
74LVT16374ADGG,518	NXP	获取价格	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP 48
74LVT16374ADL	NXP	获取价格	3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State
74LVT16374ADL,112	NXP	获取价格	74LVT16374A; 74LVTH16374A - 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state SSOP 48-
74LVT16374ADL-T	ETC	获取价格	16-Bit D-Type Flip-Flop

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